#include "raster-helpers.h"
Include dependency graph for raster-expected-phase3.h:
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Macros | |
| #define | EXPECT_NV1_PIXEL_0_0 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_NV1_PIXEL_0_5 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 mid-column */ |
| #define | EXPECT_NV1_PIXEL_0_9 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 last row */ |
| #define | EXPECT_NV1_PIXEL_0_10 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom excluded */ |
| #define | EXPECT_NV1_PIXEL_1_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge excluded */ |
| #define | EXPECT_NV2_PIXEL_0_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 top-row apex dropped */ |
| #define | EXPECT_NV2_PIXEL_0_1 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 narrow row KEPT (not just top-row) */ |
| #define | EXPECT_NV2_PIXEL_0_5 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 mid */ |
| #define | EXPECT_NV2_PIXEL_0_9 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_NV2_PIXEL_1_9 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 widest row */ |
| #define | EXPECT_NV2_PIXEL_2_9 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge */ |
| #define | EXPECT_NV3_PIXEL_5_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_NV3_PIXEL_5_10 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_NV3_PIXEL_5_19 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 last row */ |
| #define | EXPECT_NV3_PIXEL_5_20 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom */ |
| #define | EXPECT_NV3_PIXEL_6_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge */ |
| #define | EXPECT_NV3_PIXEL_4_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 before left */ |
| #define | EXPECT_NH1_PIXEL_0_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_NH1_PIXEL_10_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_NH1_PIXEL_19_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 last x */ |
| #define | EXPECT_NH1_PIXEL_20_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge */ |
| #define | EXPECT_NH1_PIXEL_0_1 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom */ |
| #define | EXPECT_NH2_PIXEL_0_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 top-row apex */ |
| #define | EXPECT_NH2_PIXEL_10_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_NH3_PIXEL_0_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_NH3_PIXEL_20_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_NH3_PIXEL_39_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 last x */ |
| #define | EXPECT_NH3_PIXEL_40_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right vertex */ |
| #define | EXPECT_NH3_PIXEL_20_1 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom */ |
| #define | EXPECT_LE1_PIXEL_0_0 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 top-left corner */ |
| #define | EXPECT_LE1_PIXEL_5_4 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 interior */ |
| #define | EXPECT_LE1_PIXEL_9_0 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 right end of top edge */ |
| #define | EXPECT_LE1_PIXEL_10_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right-vertex top */ |
| #define | EXPECT_LE1_PIXEL_5_9 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 apex - bottom convention */ |
| #define | EXPECT_LE2_PIXEL_0_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_LE2_PIXEL_19_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 right end of top edge */ |
| #define | EXPECT_LE2_PIXEL_10_4 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 near apex */ |
| #define | EXPECT_LE2_PIXEL_10_5 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 apex - bottom convention */ |
| #define | EXPECT_LE3_PIXEL_0_0 RASTER_VRAM_WHITE /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_LE3_PIXEL_2_0 RASTER_VRAM_WHITE /* HW_VERIFIED 2026-05-15 last x on top */ |
| #define | EXPECT_LE3_PIXEL_3_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right-vertex of top */ |
| #define | EXPECT_LE3_PIXEL_5_10 RASTER_VRAM_WHITE /* HW_VERIFIED 2026-05-15 mid-interior */ |
| #define | EXPECT_LE3_PIXEL_10_20 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 apex */ |
| #define | EXPECT_SF1_PIXEL_0_0 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_SF1_PIXEL_2_0 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 last x top */ |
| #define | EXPECT_SF1_PIXEL_2_1 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 fractional right */ |
| #define | EXPECT_SF1_PIXEL_2_2 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_SF1_PIXEL_2_3 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right=2 exact, x=2 excluded */ |
| #define | EXPECT_SF1_PIXEL_1_3 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_SF1_PIXEL_1_6 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right=1 exact, x=1 excluded */ |
| #define | EXPECT_SF1_PIXEL_0_6 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_SF1_PIXEL_0_7 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 narrow rows are KEPT past the apex */ |
| #define | EXPECT_SF1_PIXEL_0_8 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 same */ |
| #define | EXPECT_SF2_PIXEL_0_0 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 1px column kept */ |
| #define | EXPECT_SF2_PIXEL_0_1 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_SF2_PIXEL_0_4 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_SF3_PIXEL_0_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_SF3_PIXEL_2_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_SF3_PIXEL_2_1 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 interpolated edge */ |
| #define | EXPECT_SF3_PIXEL_2_2 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 right=2.143 -> x=2 KEPT */ |
| #define | EXPECT_SF3_PIXEL_1_2 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_SF3_PIXEL_0_3 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_SF3_PIXEL_1_3 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 right=1.714 -> x=1 KEPT */ |
| #define | EXPECT_SF3_PIXEL_0_5 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 narrow KEPT */ |
| #define | EXPECT_QS1_PIXEL_0_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_QS1_PIXEL_7_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 top right interior */ |
| #define | EXPECT_QS1_PIXEL_8_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 vertex 1 - might be top-right corner */ |
| #define | EXPECT_QS1_PIXEL_4_4 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 mid-quad on seam */ |
| #define | EXPECT_QS1_PIXEL_1_7 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 near vertex 2 */ |
| #define | EXPECT_QS1_PIXEL_8_7 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 bottom-right interior */ |
| #define | EXPECT_QS1_PIXEL_0_7 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 outside-left of seam triangle */ |
| #define | EXPECT_QS1_PIXEL_1_8 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom edge */ |
| #define | EXPECT_QS2_PIXEL_0_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_QS2_PIXEL_5_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
| #define | EXPECT_QS2_PIXEL_9_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 right-end top */ |
| #define | EXPECT_QS2_PIXEL_10_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 vertex */ |
| #define | EXPECT_QS2_PIXEL_2_5 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 seam gap */ |
| #define | EXPECT_QS2_PIXEL_12_5 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 mid-right interior */ |
| #define | EXPECT_QS2_PIXEL_5_9 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 near vertex 2 */ |
| #define | EXPECT_QS2_PIXEL_5_10 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom */ |
Macro Definition Documentation
◆ EXPECT_LE1_PIXEL_0_0
| #define EXPECT_LE1_PIXEL_0_0 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 top-left corner */ |
◆ EXPECT_LE1_PIXEL_10_0
| #define EXPECT_LE1_PIXEL_10_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right-vertex top */ |
◆ EXPECT_LE1_PIXEL_5_4
| #define EXPECT_LE1_PIXEL_5_4 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 interior */ |
◆ EXPECT_LE1_PIXEL_5_9
| #define EXPECT_LE1_PIXEL_5_9 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 apex - bottom convention */ |
◆ EXPECT_LE1_PIXEL_9_0
| #define EXPECT_LE1_PIXEL_9_0 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 right end of top edge */ |
◆ EXPECT_LE2_PIXEL_0_0
| #define EXPECT_LE2_PIXEL_0_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_LE2_PIXEL_10_4
| #define EXPECT_LE2_PIXEL_10_4 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 near apex */ |
◆ EXPECT_LE2_PIXEL_10_5
| #define EXPECT_LE2_PIXEL_10_5 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 apex - bottom convention */ |
◆ EXPECT_LE2_PIXEL_19_0
| #define EXPECT_LE2_PIXEL_19_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 right end of top edge */ |
◆ EXPECT_LE3_PIXEL_0_0
| #define EXPECT_LE3_PIXEL_0_0 RASTER_VRAM_WHITE /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_LE3_PIXEL_10_20
| #define EXPECT_LE3_PIXEL_10_20 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 apex */ |
◆ EXPECT_LE3_PIXEL_2_0
| #define EXPECT_LE3_PIXEL_2_0 RASTER_VRAM_WHITE /* HW_VERIFIED 2026-05-15 last x on top */ |
◆ EXPECT_LE3_PIXEL_3_0
| #define EXPECT_LE3_PIXEL_3_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right-vertex of top */ |
◆ EXPECT_LE3_PIXEL_5_10
| #define EXPECT_LE3_PIXEL_5_10 RASTER_VRAM_WHITE /* HW_VERIFIED 2026-05-15 mid-interior */ |
◆ EXPECT_NH1_PIXEL_0_0
| #define EXPECT_NH1_PIXEL_0_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_NH1_PIXEL_0_1
| #define EXPECT_NH1_PIXEL_0_1 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom */ |
◆ EXPECT_NH1_PIXEL_10_0
| #define EXPECT_NH1_PIXEL_10_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_NH1_PIXEL_19_0
| #define EXPECT_NH1_PIXEL_19_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 last x */ |
◆ EXPECT_NH1_PIXEL_20_0
| #define EXPECT_NH1_PIXEL_20_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge */ |
◆ EXPECT_NH2_PIXEL_0_0
| #define EXPECT_NH2_PIXEL_0_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 top-row apex */ |
◆ EXPECT_NH2_PIXEL_10_0
| #define EXPECT_NH2_PIXEL_10_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_NH3_PIXEL_0_0
| #define EXPECT_NH3_PIXEL_0_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_NH3_PIXEL_20_0
| #define EXPECT_NH3_PIXEL_20_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_NH3_PIXEL_20_1
| #define EXPECT_NH3_PIXEL_20_1 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom */ |
◆ EXPECT_NH3_PIXEL_39_0
| #define EXPECT_NH3_PIXEL_39_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 last x */ |
◆ EXPECT_NH3_PIXEL_40_0
| #define EXPECT_NH3_PIXEL_40_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right vertex */ |
◆ EXPECT_NV1_PIXEL_0_0
| #define EXPECT_NV1_PIXEL_0_0 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_NV1_PIXEL_0_10
| #define EXPECT_NV1_PIXEL_0_10 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom excluded */ |
◆ EXPECT_NV1_PIXEL_0_5
| #define EXPECT_NV1_PIXEL_0_5 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 mid-column */ |
◆ EXPECT_NV1_PIXEL_0_9
| #define EXPECT_NV1_PIXEL_0_9 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 last row */ |
◆ EXPECT_NV1_PIXEL_1_0
| #define EXPECT_NV1_PIXEL_1_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge excluded */ |
◆ EXPECT_NV2_PIXEL_0_0
| #define EXPECT_NV2_PIXEL_0_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 top-row apex dropped */ |
◆ EXPECT_NV2_PIXEL_0_1
| #define EXPECT_NV2_PIXEL_0_1 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 narrow row KEPT (not just top-row) */ |
◆ EXPECT_NV2_PIXEL_0_5
| #define EXPECT_NV2_PIXEL_0_5 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 mid */ |
◆ EXPECT_NV2_PIXEL_0_9
| #define EXPECT_NV2_PIXEL_0_9 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_NV2_PIXEL_1_9
| #define EXPECT_NV2_PIXEL_1_9 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 widest row */ |
◆ EXPECT_NV2_PIXEL_2_9
| #define EXPECT_NV2_PIXEL_2_9 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge */ |
◆ EXPECT_NV3_PIXEL_4_0
| #define EXPECT_NV3_PIXEL_4_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 before left */ |
◆ EXPECT_NV3_PIXEL_5_0
| #define EXPECT_NV3_PIXEL_5_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_NV3_PIXEL_5_10
| #define EXPECT_NV3_PIXEL_5_10 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_NV3_PIXEL_5_19
| #define EXPECT_NV3_PIXEL_5_19 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 last row */ |
◆ EXPECT_NV3_PIXEL_5_20
| #define EXPECT_NV3_PIXEL_5_20 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom */ |
◆ EXPECT_NV3_PIXEL_6_0
| #define EXPECT_NV3_PIXEL_6_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge */ |
◆ EXPECT_QS1_PIXEL_0_0
| #define EXPECT_QS1_PIXEL_0_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_QS1_PIXEL_0_7
| #define EXPECT_QS1_PIXEL_0_7 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 outside-left of seam triangle */ |
◆ EXPECT_QS1_PIXEL_1_7
| #define EXPECT_QS1_PIXEL_1_7 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 near vertex 2 */ |
◆ EXPECT_QS1_PIXEL_1_8
| #define EXPECT_QS1_PIXEL_1_8 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom edge */ |
◆ EXPECT_QS1_PIXEL_4_4
| #define EXPECT_QS1_PIXEL_4_4 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 mid-quad on seam */ |
◆ EXPECT_QS1_PIXEL_7_0
| #define EXPECT_QS1_PIXEL_7_0 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 top right interior */ |
◆ EXPECT_QS1_PIXEL_8_0
| #define EXPECT_QS1_PIXEL_8_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 vertex 1 - might be top-right corner */ |
◆ EXPECT_QS1_PIXEL_8_7
| #define EXPECT_QS1_PIXEL_8_7 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 bottom-right interior */ |
◆ EXPECT_QS2_PIXEL_0_0
| #define EXPECT_QS2_PIXEL_0_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_QS2_PIXEL_10_0
| #define EXPECT_QS2_PIXEL_10_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 vertex */ |
◆ EXPECT_QS2_PIXEL_12_5
| #define EXPECT_QS2_PIXEL_12_5 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 mid-right interior */ |
◆ EXPECT_QS2_PIXEL_2_5
| #define EXPECT_QS2_PIXEL_2_5 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 seam gap */ |
◆ EXPECT_QS2_PIXEL_5_0
| #define EXPECT_QS2_PIXEL_5_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_QS2_PIXEL_5_10
| #define EXPECT_QS2_PIXEL_5_10 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom */ |
◆ EXPECT_QS2_PIXEL_5_9
| #define EXPECT_QS2_PIXEL_5_9 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 near vertex 2 */ |
◆ EXPECT_QS2_PIXEL_9_0
| #define EXPECT_QS2_PIXEL_9_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 right-end top */ |
◆ EXPECT_SF1_PIXEL_0_0
| #define EXPECT_SF1_PIXEL_0_0 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_SF1_PIXEL_0_6
| #define EXPECT_SF1_PIXEL_0_6 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_SF1_PIXEL_0_7
| #define EXPECT_SF1_PIXEL_0_7 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 narrow rows are KEPT past the apex */ |
◆ EXPECT_SF1_PIXEL_0_8
| #define EXPECT_SF1_PIXEL_0_8 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 same */ |
◆ EXPECT_SF1_PIXEL_1_3
| #define EXPECT_SF1_PIXEL_1_3 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_SF1_PIXEL_1_6
| #define EXPECT_SF1_PIXEL_1_6 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right=1 exact, x=1 excluded */ |
◆ EXPECT_SF1_PIXEL_2_0
| #define EXPECT_SF1_PIXEL_2_0 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 last x top */ |
◆ EXPECT_SF1_PIXEL_2_1
| #define EXPECT_SF1_PIXEL_2_1 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 fractional right */ |
◆ EXPECT_SF1_PIXEL_2_2
| #define EXPECT_SF1_PIXEL_2_2 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_SF1_PIXEL_2_3
| #define EXPECT_SF1_PIXEL_2_3 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right=2 exact, x=2 excluded */ |
◆ EXPECT_SF2_PIXEL_0_0
| #define EXPECT_SF2_PIXEL_0_0 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 1px column kept */ |
◆ EXPECT_SF2_PIXEL_0_1
| #define EXPECT_SF2_PIXEL_0_1 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_SF2_PIXEL_0_4
| #define EXPECT_SF2_PIXEL_0_4 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_SF3_PIXEL_0_0
| #define EXPECT_SF3_PIXEL_0_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_SF3_PIXEL_0_3
| #define EXPECT_SF3_PIXEL_0_3 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_SF3_PIXEL_0_5
| #define EXPECT_SF3_PIXEL_0_5 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 narrow KEPT */ |
◆ EXPECT_SF3_PIXEL_1_2
| #define EXPECT_SF3_PIXEL_1_2 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_SF3_PIXEL_1_3
| #define EXPECT_SF3_PIXEL_1_3 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 right=1.714 -> x=1 KEPT */ |
◆ EXPECT_SF3_PIXEL_2_0
| #define EXPECT_SF3_PIXEL_2_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_SF3_PIXEL_2_1
| #define EXPECT_SF3_PIXEL_2_1 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 interpolated edge */ |
◆ EXPECT_SF3_PIXEL_2_2
| #define EXPECT_SF3_PIXEL_2_2 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 right=2.143 -> x=2 KEPT */ |
