42#define MASK_SUITE_SENTINEL 0x5555u
47static void rasterDrawMaskSet(
void) {
57 rasterFlushPrimitive();
65static void rasterDrawMaskCheck(
void) {
72 rasterFlushPrimitive();
77 rasterFlushPrimitive();
89CESTER_TEST(maskSet_origin_has_mask_bit, gpu_raster_phase2,
94CESTER_TEST(maskSet_interior_has_mask_bit, gpu_raster_phase2,
99CESTER_TEST(maskSet_right_edge_excluded, gpu_raster_phase2,
111CESTER_TEST(maskCheck_preserves_red_at_overlap_1_0, gpu_raster_phase2,
112 rasterDrawMaskCheck();
119CESTER_TEST(maskCheck_fills_green_in_non_overlap_5_0, gpu_raster_phase2,
120 rasterDrawMaskCheck();
CESTER_BODY(static int s_got40;static int s_got80;static uint32_t s_cause;static uint32_t s_epc;static uint32_t s_from;static uint32_t *s_resume;static uint32_t *s_regs;static uint32_t(*s_customhandler)()=NULL;static uint32_t s_oldIMASK;static uint32_t s_oldDPCR;static uint32_t s_oldDICR;uint32_t handler(uint32_t *regs, uint32_t from) { if(from==0x40) s_got40=1;if(from==0x80) s_got80=1;uint32_t cause;uint32_t epc;s_from=from;asm("mfc0 %0, $13\nnop\nmfc0 %1, $14\nnop" :"=r"(cause), "=r"(epc));s_cause=cause;s_epc=epc;if(s_customhandler) { return s_customhandler();} else { return s_resume ?((uint32_t) s_resume) :(epc+4);} } void installExceptionHandlers(uint32_t(*handler)(uint32_t *regs, uint32_t from));void uninstallExceptionHandlers();uint32_t branchbranch1();uint32_t branchbranch2();uint32_t jumpjump1();uint32_t jumpjump2();uint32_t cpu_LWR_LWL_half(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_nodelay(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_delayed(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_load_different(uint32_t buff[], uint32_t initial);uint32_t cpu_LW_LWR(uint32_t buff[], uint32_t initial);uint32_t cpu_delayed_load(uint32_t buff[], uint32_t override);uint32_t cpu_delayed_load_cancelled(uint32_t buff[], uint32_t override);uint64_t cpu_delayed_load_load(uint32_t buff[], uint32_t override);uint32_t linkandload();uint32_t lwandlink();uint32_t nolink();static int s_interruptsWereEnabled;) CESTER_BEFORE_EACH(cpu_tests
CESTER_TEST(cpu_cop0_basic_write_bp, cpu_tests, uint32_t expectedEPC;uint32_t t;volatile uint32_t *ptr=(volatile uint32_t *) 0x58; *ptr=1;__asm__ volatile("" " lui %0, 0b1100101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0xfffffff0\n" " mtc0 %0, $9\n" :"=r"(t));cester_assert_uint_eq(1, *ptr);__asm__ volatile("la %0, 1f\n1:\nsw $0, 0x58($0)" :"=r"(expectedEPC));__asm__ volatile("mtc0 $0, $7\n");cester_assert_uint_eq(0, *ptr);cester_assert_uint_eq(1, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0x40, s_from);cester_assert_uint_eq(expectedEPC, s_epc);) CESTER_TEST(cpu_cop0_kseg_write_bp
#define MASK_SUITE_SENTINEL
Definition mask-bit.c:42
#define EXPECT_MASK_CHECK_PIXEL_5_0_filled
Definition raster-expected-phase2.h:115
#define EXPECT_MASK_SET_PIXEL_0_0
Definition raster-expected-phase2.h:101
#define EXPECT_MASK_SET_PIXEL_2_1
Definition raster-expected-phase2.h:102
#define EXPECT_MASK_CHECK_PIXEL_1_0_preserved
Definition raster-expected-phase2.h:114
#define RASTER_CMD_RED
Definition raster-helpers.h:123
#define RASTER_CMD_GREEN
Definition raster-helpers.h:125
#define ASSERT_PIXEL_EQ(expected, x_, y_)
Definition raster-helpers.h:472