cop0.c File Reference

#include "common/hardware/dma.h"
#include "common/hardware/hwregs.h"
#include "common/syscalls/syscalls.h"
#include "exotic/cester.h"
#include "cester-cop0.c"

Include dependency graph for cop0.c:

Macros
#define	PCSX_TESTS   0
#define	CESTER_MAYBE_TEST   CESTER_TEST
#define	CESTER_NO_SIGNAL
#define	CESTER_NO_TIME
#define	EXIT_SUCCESS   0
#define	EXIT_FAILURE   1

Functions
	CESTER_TEST (cpu_cop0_basic_write_bp, cpu_tests, uint32_t expectedEPC;uint32_t t;volatile uint32_t *ptr=(volatile uint32_t *) 0x58; *ptr=1;__asm__ volatile("" " lui %0, 0b1100101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0xfffffff0\n" " mtc0 %0, $9\n" :"=r"(t));cester_assert_uint_eq(1, *ptr);__asm__ volatile("la %0, 1f\n1:\nsw $0, 0x58($0)" :"=r"(expectedEPC));__asm__ volatile("mtc0 $0, $7\n");cester_assert_uint_eq(0, *ptr);cester_assert_uint_eq(1, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0x40, s_from);cester_assert_uint_eq(expectedEPC, s_epc);) CESTER_TEST(cpu_cop0_kseg_write_bp
__asm__	volatile ("" " lui %0, 0b1100101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0xfffffff0\n" " mtc0 %0, $9\n" :"=r"(t))
	cester_assert_uint_eq (1, *ptr)
__asm__	volatile ("lui $at, 0x8000\nsw $0, 0x58($at)")
__asm__	volatile ("mtc0 $0, $7\n")
	cester_assert_uint_eq (0, *ptr)
	cester_assert_uint_eq (0, s_got40)
	cester_assert_uint_eq (0, s_got80)
	cester_assert_uint_eq (0, s_from)
	cester_assert_uint_eq (0, s_epc)
	CESTER_TEST (cpu_cop0_kseg_write_bp_kd_clear, cpu_tests, uint32_t t;volatile uint32_t *ptr=(volatile uint32_t *) 0x80000058; *ptr=1;__asm__ volatile("" " lui %0, 0b1100101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0x1fffffff\n" " mtc0 %0, $9\n" :"=r"(t));cester_assert_uint_eq(1, *ptr);__asm__ volatile("lui $at, 0x8000\nsw $0, 0x58($at)");__asm__ volatile("mtc0 $0, $7\n");cester_assert_uint_eq(0, *ptr);cester_assert_uint_eq(0, s_got40);cester_assert_uint_eq(0, s_got80);) CESTER_TEST(cpu_cop0_kseg_write_bp_kd_set
__asm__	volatile ("" " lui %0, 0b1110101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0x1fffffff\n" " mtc0 %0, $9\n" :"=r"(t))
__asm__	volatile ("lui $at, 0x8000\nla %0, 1f\n1:\nsw $0, 0x58($at)" :"=r"(expectedEPC))
	cester_assert_uint_eq (1, s_got40)
	cester_assert_uint_eq (0x40, s_from)
	cester_assert_uint_eq (expectedEPC, s_epc)
	CESTER_TEST (cpu_cop0_upper_memory_write_bp, cpu_tests, uint32_t t;volatile uint32_t *ptr=(volatile uint32_t *) 0x00200058; *ptr=1;__asm__ volatile("" " lui %0, 0b1100101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0xfffffff0\n" " mtc0 %0, $9\n" :"=r"(t));cester_assert_uint_eq(1, *ptr);__asm__ volatile("lui $at, 0x0020\nsw $0, 0x58($at)");__asm__ volatile("mtc0 $0, $7\n");cester_assert_uint_eq(0, *ptr);cester_assert_uint_eq(0, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0, s_from);cester_assert_uint_eq(0, s_epc);) CESTER_TEST(cpu_cop0_unaligned_write_bp
	cester_assert_uint_eq (0x01020304, *ptr)
__asm__	volatile ("la %0, 1f\n1:\nsb $0, 0x59($0)" :"=r"(expectedEPC))
	cester_assert_uint_eq (0x01020004, *ptr)
	CESTER_TEST (cpu_unaligned_write_fault, CESTER_MAYBE_TEST(cpu_tests, uint32_t expectedEPC;__asm__ volatile("la %0, 1f\n1:\nsw $0, 1($0)" :"=r"(expectedEPC));cester_assert_uint_eq(0, s_got40);cester_assert_uint_eq(1, s_got80);cester_assert_uint_eq(0x80, s_from);cester_assert_uint_eq(expectedEPC, s_epc);)
	cester_assert_uint_eq (0xf04fff3d, mask)
	CESTER_MAYBE_TEST (cpu_cop0_cu1_unusable, cpu_tests, uint32_t old, sr;__asm__ volatile("mfc0 %0, $12\nnop" :"=r"(old));sr=old &~0x20000000;__asm__ volatile("mtc0 %0, $12\nnop\nnop" ::"r"(sr));__asm__ volatile(".word 0x44080000" :::"t0");__asm__ volatile("mtc0 %0, $12\nnop\nnop" ::"r"(old));cester_assert_uint_eq(1, s_got80);uint32_t ce=s_cause &0x3000007c;cester_assert_uint_eq(0x1000002c, ce);) CESTER_MAYBE_TEST(cpu_cop0_cu3_unusable
__asm__	volatile ("mfc0 %0, $12\nnop" :"=r"(old))
__asm__	volatile ("mtc0 %0, $12\nnop\nnop" ::"r"(sr))
__asm__	volatile (".word 0x4c080000" :::"t0")
__asm__	volatile ("mtc0 %0, $12\nnop\nnop" ::"r"(old))
	cester_assert_uint_eq (1, s_got80)
	cester_assert_uint_eq (0x3000002c, ce)
	CESTER_TEST (cpu_ADD_overflow_in_delay_slot, CESTER_TEST(cpu_tests, s_resume=(uint32_t *) delayslot_resume;uint32_t branch=delayslot_add();uint32_t excode=(s_cause > > 2) &0x1f;uint32_t bd=s_cause > > 31;cester_assert_uint_eq(1, s_got80);cester_assert_uint_eq(12, excode);cester_assert_uint_eq(1, bd);cester_assert_uint_eq(branch, s_epc);)
	CESTER_TEST (cpu_software_interrupt, cpu_tests, uint32_t sr;__asm__ volatile("mfc0 %0, $12\nnop" :"=r"(sr));s_customhandler=delayslot_clear_cause;__asm__ volatile("mtc0 %0, $12\nnop\nnop" ::"r"((sr &~0xff00)|0x101));uint32_t next=plain_swi();__asm__ volatile("mtc0 %0, $12\nnop\nnop" ::"r"(sr));s_customhandler=NULL;uint32_t excode=(s_cause > > 2) &0x1f;uint32_t bd=s_cause > > 31;cester_assert_uint_eq(1, s_got80);cester_assert_uint_eq(0, excode);cester_assert_uint_eq(0, bd);cester_assert_uint_eq(next, s_epc);cester_assert_uint_eq(0, delayslot_taken);) CESTER_TEST(cpu_software_interrupt_in_delay_slot
__asm__	volatile ("mtc0 %0, $12\nnop\nnop" ::"r"((sr &~0xff00)|0x101))
	delayslot_swi ()
	cester_assert_uint_eq (0, excode)
	cester_assert_uint_eq (0, bd)
	cester_assert_uint_eq ((uint32_t) delayslot_mark, s_epc)
	cester_assert_uint_eq (0, delayslot_taken)

Variables
	cpu_tests
uint32_t	t
volatile uint32_t *	ptr = (volatile uint32_t *) 0x80000058
uint32_t	expectedEPC
uint32_t	old
uint32_t	sr = old & ~0x80000000
uint32_t	ce = s_cause & 0x3000007c
	s_customhandler = delayslot_clear_cause
uint32_t	excode = (s_cause >> 2) & 0x1f
uint32_t	bd = s_cause >> 31

Macro Definition Documentation

CESTER_MAYBE_TEST

#define CESTER_MAYBE_TEST   CESTER_TEST

CESTER_NO_SIGNAL

#define CESTER_NO_SIGNAL

CESTER_NO_TIME

#define CESTER_NO_TIME

EXIT_FAILURE

#define EXIT_FAILURE   1

EXIT_SUCCESS

#define EXIT_SUCCESS   0

PCSX_TESTS

#define PCSX_TESTS   0

Function Documentation

cester_assert_uint_eq() [1/18]

cester_assert_uint_eq	(	(uint32_t)	delayslot_mark,
		s_epc
	)

cester_assert_uint_eq() [2/18]

cester_assert_uint_eq	(	0	,
		*	ptr
	)

cester_assert_uint_eq() [3/18]

cester_assert_uint_eq	(	0	,
		bd
	)

cester_assert_uint_eq() [4/18]

cester_assert_uint_eq	(	0	,
		delayslot_taken
	)

cester_assert_uint_eq() [5/18]

cester_assert_uint_eq	(	0	,
		excode
	)

cester_assert_uint_eq() [6/18]

cester_assert_uint_eq	(	0	,
		s_epc
	)

cester_assert_uint_eq() [7/18]

cester_assert_uint_eq	(	0	,
		s_from
	)

cester_assert_uint_eq() [8/18]

cester_assert_uint_eq	(	0	,
		s_got40
	)

cester_assert_uint_eq() [9/18]

cester_assert_uint_eq	(	0	,
		s_got80
	)

cester_assert_uint_eq() [10/18]

cester_assert_uint_eq	(	0x01020004	,
		*	ptr
	)

cester_assert_uint_eq() [11/18]

cester_assert_uint_eq	(	0x01020304	,
		*	ptr
	)

cester_assert_uint_eq() [12/18]

cester_assert_uint_eq	(	0x3000002c	,
		ce
	)

cester_assert_uint_eq() [13/18]

cester_assert_uint_eq	(	0x40	,
		s_from
	)

cester_assert_uint_eq() [14/18]

cester_assert_uint_eq	(	0xf04fff3d	,
		mask
	)

cester_assert_uint_eq() [15/18]

cester_assert_uint_eq	(	1	,
		*	ptr
	)

cester_assert_uint_eq() [16/18]

cester_assert_uint_eq	(	1	,
		s_got40
	)

cester_assert_uint_eq() [17/18]

cester_assert_uint_eq	(	1	,
		s_got80
	)

cester_assert_uint_eq() [18/18]

cester_assert_uint_eq	(	expectedEPC	,
		s_epc
	)

CESTER_MAYBE_TEST()

CESTER_MAYBE_TEST	(	cpu_cop0_cu1_unusable	,
		cpu_tests	,
		uint32_t	old,
		sr;__asm__ volatile("mfc0 %0, $12\nnop" :"=r"(old));	sr = old & ~0x20000000; __asm__ volatile("mtc0 %0, $12\nnop\nnop" : : "r"(sr)); __asm__ volatile(".word 0x44080000" : : : "t0"); __asm__ volatile("mtc0 %0, $12\nnop\nnop" : : "r"(old)); cester_assert_uint_eq(1, s_got80); uint32_t ce = s_cause & 0x3000007c; cester_assert_uint_eq(0x1000002c, ce);
	)

CESTER_TEST() [1/6]

CESTER_TEST	(	cpu_ADD_overflow_in_delay_slot	,
		CESTER_TEST(	cpu_tests,
		s_resume	= (uint32_t *)delayslot_resume; uint32_t branch = delayslot_add(); uint32_t excode = (s_cause >> 2) & 0x1f; uint32_t bd = s_cause >> 31; cester_assert_uint_eq(1, s_got80); cester_assert_uint_eq(12, excode); cester_assert_uint_eq(1, bd); cester_assert_uint_eq(branch, s_epc);
	)

CESTER_TEST() [2/6]

CESTER_TEST	(	cpu_cop0_basic_write_bp	,
		cpu_tests	,
		uint32_t expectedEPC;uint32_t t;volatile uint32_t *	ptr = (volatile uint32_t *) 0x58; *ptr = 1; __asm__ volatile("""    lui   %0, 0b1100101010000000\n""    mtc0  %0, $7\n""    li    %0, 0x58\n""    mtc0  %0, $5\n""    li    %0, 0xfffffff0\n""    mtc0  %0, $9\n" : "=r"(t)); cester_assert_uint_eq(1, *ptr); __asm__ volatile("la %0, 1f\n1:\nsw $0, 0x58($0)" : "=r"(expectedEPC)); __asm__ volatile("mtc0 $0, $7\n"); cester_assert_uint_eq(0, *ptr); cester_assert_uint_eq(1, s_got40); cester_assert_uint_eq(0, s_got80); cester_assert_uint_eq(0x40, s_from); cester_assert_uint_eq(expectedEPC, s_epc);
	)

CESTER_TEST() [3/6]

CESTER_TEST	(	cpu_cop0_kseg_write_bp_kd_clear	,
		cpu_tests	,
		uint32_t t;volatile uint32_t *	ptr = (volatile uint32_t *) 0x80000058; *ptr = 1; __asm__ volatile("""    lui   %0, 0b1100101010000000\n""    mtc0  %0, $7\n""    li    %0, 0x58\n""    mtc0  %0, $5\n""    li    %0, 0x1fffffff\n""    mtc0  %0, $9\n" : "=r"(t)); cester_assert_uint_eq(1, *ptr); __asm__ volatile("lui $at, 0x8000\nsw $0, 0x58($at)"); __asm__ volatile("mtc0 $0, $7\n"); cester_assert_uint_eq(0, *ptr); cester_assert_uint_eq(0, s_got40); cester_assert_uint_eq(0, s_got80);
	)

CESTER_TEST() [4/6]

CESTER_TEST	(	cpu_cop0_upper_memory_write_bp	,
		cpu_tests	,
		uint32_t t;volatile uint32_t *	ptr = (volatile uint32_t *) 0x00200058; *ptr = 1; __asm__ volatile("""    lui   %0, 0b1100101010000000\n""    mtc0  %0, $7\n""    li    %0, 0x58\n""    mtc0  %0, $5\n""    li    %0, 0xfffffff0\n""    mtc0  %0, $9\n" : "=r"(t)); cester_assert_uint_eq(1, *ptr); __asm__ volatile("lui $at, 0x0020\nsw $0, 0x58($at)"); __asm__ volatile("mtc0 $0, $7\n"); cester_assert_uint_eq(0, *ptr); cester_assert_uint_eq(0, s_got40); cester_assert_uint_eq(0, s_got80); cester_assert_uint_eq(0, s_from); cester_assert_uint_eq(0, s_epc);
	)

CESTER_TEST() [5/6]

CESTER_TEST	(	cpu_software_interrupt	,
		cpu_tests	,
		uint32_t sr;__asm__ volatile("mfc0 %0, $12\nnop" :"=r"(sr));	s_customhandler = delayslot_clear_cause; __asm__ volatile("mtc0 %0, $12\nnop\nnop" : : "r"((sr & ~0xff00) | 0x101)); uint32_t next = plain_swi(); __asm__ volatile("mtc0 %0, $12\nnop\nnop" : : "r"(sr)); s_customhandler = NULL; uint32_t excode = (s_cause >> 2) & 0x1f; uint32_t bd = s_cause >> 31; cester_assert_uint_eq(1, s_got80); cester_assert_uint_eq(0, excode); cester_assert_uint_eq(0, bd); cester_assert_uint_eq(next, s_epc); cester_assert_uint_eq(0, delayslot_taken);
	)

CESTER_TEST() [6/6]

CESTER_TEST	(	cpu_unaligned_write_fault	,
		CESTER_MAYBE_TEST(	cpu_tests,
		uint32_t expectedEPC;__asm__ volatile("la %0, 1f\n1:\nsw $0, 1($0)" :"=r"(expectedEPC));cester_assert_uint_eq(0, s_got40);cester_assert_uint_eq(1, s_got80);cester_assert_uint_eq(0x80, s_from);cester_assert_uint_eq(expectedEPC, s_epc);
	)

delayslot_swi()

delayslot_swi

(

)

volatile() [1/11]

__asm__ volatile	(	"" " lui %	0,
		0b1100101010000000\n" " mtc0 %	0,
			$7\n" " li %,
		0x58\n" " mtc0 %	0,
			$5\n" " li %,
		0xfffffff0\n" " mtc0 %	0
	)

volatile() [2/11]

__asm__ volatile	(	"" " lui %	0,
		0b1110101010000000\n" " mtc0 %	0,
			$7\n" " li %,
		0x58\n" " mtc0 %	0,
			$5\n" " li %,
		0x1fffffff\n" " mtc0 %	0
	)

volatile() [3/11]

__asm__ volatile

(

".word 0x4c080000" :::"t0"

)

volatile() [4/11]

__asm__ volatile	(	"la %	0,
		1f\n1:\nsb	$0
	)

volatile() [5/11]

__asm__ volatile	(	"lui	$at,
		0x8000\nla %	0,
		1f\n1:\nsw	$0
	)

volatile() [6/11]

__asm__ volatile	(	"lui	$at,
		0x8000\nsw	$0,
		0x58($at)"
	)

volatile() [7/11]

__asm__ volatile

(

"mfc0 %

0

)

volatile() [8/11]

__asm__ volatile	(	"mtc0	$0,
			$7\n"
	)

volatile() [9/11]

__asm__ volatile	(	"mtc0 %	0,
		$12\nnop\nnop" ::"r"	(sr &~0xff00)|0x101
	)

volatile() [10/11]

__asm__ volatile	(	"mtc0 %	0,
		$12\nnop\nnop" ::"r"	old
	)

volatile() [11/11]

__asm__ volatile	(	"mtc0 %	0,
		$12\nnop\nnop" ::"r"	sr
	)

Variable Documentation

bd

uint32_t bd = s_cause >> 31

ce

uint32_t ce = s_cause & 0x3000007c

cpu_tests

cpu_tests

excode

uint32_t excode = (s_cause >> 2) & 0x1f

expectedEPC

uint32_t expectedEPC

old

uint32_t old

ptr

* ptr = (volatile uint32_t *) 0x80000058

s_customhandler

s_customhandler = delayslot_clear_cause

sr

uint32_t sr = old & ~0x80000000

t

uint32_t t