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◆ EXPECT_LINE_D45_PIXEL_10_10
| #define EXPECT_LINE_D45_PIXEL_10_10 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 end */ |
◆ EXPECT_LINE_D45_PIXEL_5_5
| #define EXPECT_LINE_D45_PIXEL_5_5 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 start */ |
◆ EXPECT_LINE_D45_PIXEL_5_6
| #define EXPECT_LINE_D45_PIXEL_5_6 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 off-diagonal */ |
◆ EXPECT_LINE_D45_PIXEL_6_5
| #define EXPECT_LINE_D45_PIXEL_6_5 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 off-diagonal */ |
◆ EXPECT_LINE_D45_PIXEL_7_7
| #define EXPECT_LINE_D45_PIXEL_7_7 RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 interior */ |
◆ EXPECT_LINE_DN45_PIXEL_10_5
| #define EXPECT_LINE_DN45_PIXEL_10_5 RASTER_VRAM_WHITE /* HW_VERIFIED 2026-05-15 end */ |
◆ EXPECT_LINE_DN45_PIXEL_5_10
| #define EXPECT_LINE_DN45_PIXEL_5_10 RASTER_VRAM_WHITE /* HW_VERIFIED 2026-05-15 start */ |
◆ EXPECT_LINE_DN45_PIXEL_7_8
| #define EXPECT_LINE_DN45_PIXEL_7_8 RASTER_VRAM_WHITE /* HW_VERIFIED 2026-05-15 interior */ |
◆ EXPECT_LINE_H_PIXEL_10_10
| #define EXPECT_LINE_H_PIXEL_10_10 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 end point (inclusive?) */ |
◆ EXPECT_LINE_H_PIXEL_11_10
| #define EXPECT_LINE_H_PIXEL_11_10 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 past end */ |
◆ EXPECT_LINE_H_PIXEL_4_10
◆ EXPECT_LINE_H_PIXEL_5_10
| #define EXPECT_LINE_H_PIXEL_5_10 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 start point */ |
◆ EXPECT_LINE_H_PIXEL_5_11
| #define EXPECT_LINE_H_PIXEL_5_11 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 below line */ |
◆ EXPECT_LINE_H_PIXEL_7_10
| #define EXPECT_LINE_H_PIXEL_7_10 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 interior */ |
◆ EXPECT_LINE_SHALLOW_PIXEL_0_0
| #define EXPECT_LINE_SHALLOW_PIXEL_0_0 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 start */ |
◆ EXPECT_LINE_SHALLOW_PIXEL_10_3
| #define EXPECT_LINE_SHALLOW_PIXEL_10_3 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 end */ |
◆ EXPECT_LINE_SHALLOW_PIXEL_2_0
| #define EXPECT_LINE_SHALLOW_PIXEL_2_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 Bresenham picks y=1 here */ |
◆ EXPECT_LINE_SHALLOW_PIXEL_5_2
| #define EXPECT_LINE_SHALLOW_PIXEL_5_2 RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 midpoint */ |
◆ EXPECT_LINE_V_PIXEL_10_10
| #define EXPECT_LINE_V_PIXEL_10_10 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 end (inclusive?) */ |
◆ EXPECT_LINE_V_PIXEL_10_11
| #define EXPECT_LINE_V_PIXEL_10_11 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 past end */ |
◆ EXPECT_LINE_V_PIXEL_10_4
| #define EXPECT_LINE_V_PIXEL_10_4 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_LINE_V_PIXEL_10_5
| #define EXPECT_LINE_V_PIXEL_10_5 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 start */ |
◆ EXPECT_LINE_V_PIXEL_10_7
| #define EXPECT_LINE_V_PIXEL_10_7 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 interior */ |
◆ EXPECT_LINE_ZERO_PIXEL_20_20
| #define EXPECT_LINE_ZERO_PIXEL_20_20 RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_LINE_ZERO_PIXEL_21_20
| #define EXPECT_LINE_ZERO_PIXEL_21_20 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_MASK_CHECK_PIXEL_1_0_preserved
| #define EXPECT_MASK_CHECK_PIXEL_1_0_preserved 0x801fu /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_MASK_CHECK_PIXEL_5_0_filled
| #define EXPECT_MASK_CHECK_PIXEL_5_0_filled RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_MASK_SET_PIXEL_0_0
| #define EXPECT_MASK_SET_PIXEL_0_0 0x801fu /* HW_VERIFIED 2026-05-15 RED OR mask bit */ |
◆ EXPECT_MASK_SET_PIXEL_2_1
| #define EXPECT_MASK_SET_PIXEL_2_1 0x801fu /* HW_VERIFIED 2026-05-15 */ |
◆ EXPECT_MASK_SET_PIXEL_4_0
| #define EXPECT_MASK_SET_PIXEL_4_0 RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge excluded */ |
