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Macros | Functions | Variables
dma.c File Reference
#include "common/hardware/dma.h"
#include "common/hardware/gpu.h"
#include "common/hardware/hwregs.h"
#include "common/hardware/irq.h"
#include "common/syscalls/syscalls.h"
#include "exotic/cester.h"
#include "../cop0/cester-cop0.c"
Include dependency graph for dma.c:

Macros

#define PCSX_TESTS   0
 
#define CESTER_MAYBE_TEST   CESTER_TEST
 
#define CESTER_NO_SIGNAL
 
#define CESTER_NO_TIME
 
#define EXIT_SUCCESS   0
 
#define EXIT_FAILURE   1
 

Functions

 CESTER_TEST (normal_dma, dma_tests, sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);DPCR=0x00000800;DICR=0x00840000;IMASK=IRQ_VBLANK|IRQ_DMA;uint32_t cmd=0xe1000555;sendGPUStatus(0x04000002);while((GPU_STATUS &0x10000000)==0);DMA_CTRL[DMA_GPU].MADR=(uintptr_t)&cmd;DMA_CTRL[DMA_GPU].BCR=0x00010001;DMA_CTRL[DMA_GPU].CHCR=0x01000201;unsigned count=0;unsigned timeout=0;while(1) { while((IREG &(IRQ_VBLANK|IRQ_DMA))==0);if(IREG &IRQ_DMA) break;IREG &=~IRQ_VBLANK;if(count++==128) { timeout=1;break;} } IREG=0;uint32_t stat=GPU_STATUS &0x000007ff;uintptr_t bcr=DMA_CTRL[DMA_GPU].BCR;uint32_t madr=DMA_CTRL[DMA_GPU].MADR;uint32_t chcr=DMA_CTRL[DMA_GPU].CHCR;uint32_t dicr=DICR;const uintptr_t expectedAddr=((uintptr_t)(&cmd+1)) &0xffffff;cester_assert_uint_eq(0, timeout);cester_assert_uint_eq(0, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0, s_from);cester_assert_uint_eq(0, s_epc);cester_assert_uint_eq(0x555, stat);cester_assert_uint_eq(1, bcr);cester_assert_uint_eq(expectedAddr, madr);cester_assert_uint_eq(0x00000201, chcr);cester_assert_uint_eq(0x84840000, dicr);DICR=(dicr &~0x7f000000)|0x04000000;dicr=DICR;cester_assert_uint_eq(0x00840000, dicr);) CESTER_TEST(normal_dma_dicr_toggle
 
 sendGPUStatus (0)
 
 sendGPUStatus (0x04000001)
 
 sendGPUData (0xe1000000)
 
 sendGPUStatus (0x04000002)
 
 while ((GPU_STATUS &0x10000000)==0)
 
 while (1)
 
 cester_assert_uint_eq (0, timeout)
 
 cester_assert_uint_eq (0, s_got40)
 
 cester_assert_uint_eq (0, s_got80)
 
 cester_assert_uint_eq (0, s_from)
 
 cester_assert_uint_eq (0, s_epc)
 
 cester_assert_uint_eq (0x555, stat)
 
 cester_assert_uint_eq (1, bcr)
 
 cester_assert_uint_eq (expectedAddr, madr)
 
 cester_assert_uint_eq (0x00000201, chcr)
 
 cester_assert_uint_eq (0x84840000, dicr)
 
 cester_assert_uint_eq (1, timeout)
 
 cester_assert_uint_eq (0x84800000, dicr)
 
 cester_assert_uint_eq (0x04000000, dicr)
 
 cester_assert_uint_eq (0x84008000, dicr)
 
 CESTER_TEST (normal_dma_with_3_upper_bits, dma_tests, sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);DPCR=0x00000800;DICR=0x00840000;IMASK=IRQ_VBLANK|IRQ_DMA;uint32_t cmd=0xe1000555;sendGPUStatus(0x04000002);while((GPU_STATUS &0x10000000)==0);DMA_CTRL[DMA_GPU].MADR=((uintptr_t)&cmd)|0xe0000000;DMA_CTRL[DMA_GPU].BCR=0x00010001;DMA_CTRL[DMA_GPU].CHCR=0x01000201;unsigned count=0;unsigned timeout=0;while(1) { while((IREG &(IRQ_VBLANK|IRQ_DMA))==0);if(IREG &IRQ_DMA) break;IREG &=~IRQ_VBLANK;if(count++==128) { timeout=1;break;} } IREG=0;uint32_t stat=GPU_STATUS &0x000007ff;uintptr_t bcr=DMA_CTRL[DMA_GPU].BCR;uint32_t madr=DMA_CTRL[DMA_GPU].MADR;uint32_t chcr=DMA_CTRL[DMA_GPU].CHCR;uint32_t dicr=DICR;const uintptr_t expectedAddr=((uintptr_t)(&cmd+1)) &0xffffff;cester_assert_uint_eq(0, timeout);cester_assert_uint_eq(0, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0, s_from);cester_assert_uint_eq(0, s_epc);cester_assert_uint_eq(0x555, stat);cester_assert_uint_eq(1, bcr);cester_assert_uint_eq(expectedAddr, madr);cester_assert_uint_eq(0x00000201, chcr);cester_assert_uint_eq(0x84840000, dicr);DICR=(dicr &~0x7f000000)|0x04000000;dicr=DICR;cester_assert_uint_eq(0x00840000, dicr);) CESTER_TEST(normal_dma_with_8_upper_bits
 
 cester_assert_uint_eq (0x00840000, dicr)
 
 CESTER_TEST (normal_dma_odd_address, dma_tests, sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);DPCR=0x00000800;DICR=0x00840000;IMASK=IRQ_VBLANK|IRQ_DMA;uint32_t cmd=0xe1000555;sendGPUStatus(0x04000002);while((GPU_STATUS &0x10000000)==0);DMA_CTRL[DMA_GPU].MADR=((uintptr_t)&cmd)|1;DMA_CTRL[DMA_GPU].BCR=0x00010001;DMA_CTRL[DMA_GPU].CHCR=0x01000201;unsigned count=0;unsigned timeout=0;while(1) { while((IREG &(IRQ_VBLANK|IRQ_DMA))==0);if(IREG &IRQ_DMA) break;IREG &=~IRQ_VBLANK;if(count++==128) { timeout=1;break;} } IREG=0;uint32_t stat=GPU_STATUS &0x000007ff;uintptr_t bcr=DMA_CTRL[DMA_GPU].BCR;uint32_t madr=DMA_CTRL[DMA_GPU].MADR;uint32_t chcr=DMA_CTRL[DMA_GPU].CHCR;uint32_t dicr=DICR;const uintptr_t expectedAddr=((uintptr_t)(&cmd+1)) &0xffffff;cester_assert_uint_eq(0, timeout);cester_assert_uint_eq(0, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0, s_from);cester_assert_uint_eq(0, s_epc);cester_assert_uint_eq(0x555, stat);cester_assert_uint_eq(1, bcr);cester_assert_uint_eq(expectedAddr, madr);cester_assert_uint_eq(0x00000201, chcr);cester_assert_uint_eq(0x84840000, dicr);DICR=(dicr &~0x7f000000)|0x04000000;dicr=DICR;cester_assert_uint_eq(0x00840000, dicr);) CESTER_TEST(linked_dma_3_links
 
 cester_assert_uint_eq (0x12345678, bcr)
 
 cester_assert_uint_eq (0x00ffffff, madr)
 
 cester_assert_uint_eq (0x00000401, chcr)
 
 CESTER_TEST (linked_dma_3_oddlinks, dma_tests, sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);DPCR=0x00000800;DICR=0x00840000;IMASK=IRQ_VBLANK|IRQ_DMA;uint32_t cmd1[2]={ 0x01000000, 0x00000000 };uint32_t cmd2[2]={ 0x01000000, 0x00000000 };uint32_t cmd3[2]={ 0x01ffffff, 0xe1000555 };cmd1[0]=(((uint32_t)&cmd2) &0xffffff)|0x01000003;cmd2[0]=(((uint32_t)&cmd3) &0xffffff)|0x01000003;sendGPUStatus(0x04000002);while((GPU_STATUS &0x10000000)==0);DMA_CTRL[DMA_GPU].MADR=(uintptr_t)&cmd1;DMA_CTRL[DMA_GPU].BCR=0x12345678;DMA_CTRL[DMA_GPU].CHCR=0x01000401;unsigned count=0;unsigned timeout=0;while(1) { while((IREG &(IRQ_VBLANK|IRQ_DMA))==0);if(IREG &IRQ_DMA) break;IREG &=~IRQ_VBLANK;if(count++==128) { timeout=1;break;} } IREG=0;uint32_t stat=GPU_STATUS &0x000007ff;uintptr_t bcr=DMA_CTRL[DMA_GPU].BCR;uint32_t madr=DMA_CTRL[DMA_GPU].MADR;uint32_t chcr=DMA_CTRL[DMA_GPU].CHCR;uint32_t dicr=DICR;cester_assert_uint_eq(0, timeout);cester_assert_uint_eq(0, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0, s_from);cester_assert_uint_eq(0, s_epc);cester_assert_uint_eq(0x555, stat);cester_assert_uint_eq(0x12345678, bcr);cester_assert_uint_eq(0x00ffffff, madr);cester_assert_uint_eq(0x00000401, chcr);cester_assert_uint_eq(0x84840000, dicr);DICR=(dicr &~0x7f000000)|0x04000000;dicr=DICR;cester_assert_uint_eq(0x00840000, dicr);) CESTER_TEST(linked_dma_ffffff_terminator
 
 CESTER_TEST (linked_dma_fffff0_terminator, dma_tests, sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);DPCR=0x00000800;DICR=0x00840000;IMASK=IRQ_VBLANK|IRQ_DMA;uint32_t cmd[2]={ 0x01fffff0, 0xe1000555 };sendGPUStatus(0x04000002);while((GPU_STATUS &0x10000000)==0);DMA_CTRL[DMA_GPU].MADR=(uintptr_t)&cmd;DMA_CTRL[DMA_GPU].BCR=0x12345678;DMA_CTRL[DMA_GPU].CHCR=0x01000401;unsigned count=0;unsigned timeout=0;while(1) { while((IREG &(IRQ_VBLANK|IRQ_DMA))==0);if(IREG &IRQ_DMA) break;IREG &=~IRQ_VBLANK;if(count++==128) { timeout=1;break;} } IREG=0;uint32_t stat=GPU_STATUS &0x000007ff;uintptr_t bcr=DMA_CTRL[DMA_GPU].BCR;uint32_t madr=DMA_CTRL[DMA_GPU].MADR;uint32_t chcr=DMA_CTRL[DMA_GPU].CHCR;uint32_t dicr=DICR;cester_assert_uint_eq(0, timeout);cester_assert_uint_eq(0, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0, s_from);cester_assert_uint_eq(0, s_epc);cester_assert_uint_eq(0x555, stat);cester_assert_uint_eq(0x12345678, bcr);cester_assert_uint_eq(0x00fffff0, madr);cester_assert_uint_eq(0x00000401, chcr);cester_assert_uint_eq(0x84848000, dicr);dicr &=0xffffff;DICR=dicr|0x04000000;dicr=DICR;cester_assert_uint_eq(0x80848000, dicr);dicr &=0xff7fff;DICR=dicr;dicr=DICR;cester_assert_uint_eq(0x00840000, dicr);) CESTER_TEST(linked_dma_800000_terminator
 
 cester_assert_uint_eq (0x00800000, madr)
 
 cester_assert_uint_eq (0x84848000, dicr)
 
 cester_assert_uint_eq (0x80848000, dicr)
 
 CESTER_TEST (linked_dma_800000_terminator_dicr_toggle, dma_tests, sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);DPCR=0x00000800;DICR=0x00840000;IMASK=IRQ_VBLANK|IRQ_DMA;uint32_t cmd[2]={ 0x01800000, 0xe1000555 };sendGPUStatus(0x04000002);while((GPU_STATUS &0x10000000)==0);DMA_CTRL[DMA_GPU].MADR=(uintptr_t)&cmd;DMA_CTRL[DMA_GPU].BCR=0x12345678;DMA_CTRL[DMA_GPU].CHCR=0x01000401;unsigned count=0;unsigned timeout=0;while(1) { while((IREG &(IRQ_VBLANK|IRQ_DMA))==0);if(IREG &IRQ_DMA) break;IREG &=~IRQ_VBLANK;if(count++==128) { timeout=1;break;} } IREG=0;uint32_t stat=GPU_STATUS &0x000007ff;uintptr_t bcr=DMA_CTRL[DMA_GPU].BCR;uint32_t madr=DMA_CTRL[DMA_GPU].MADR;uint32_t chcr=DMA_CTRL[DMA_GPU].CHCR;uint32_t dicr=DICR;cester_assert_uint_eq(0, timeout);cester_assert_uint_eq(0, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0, s_from);cester_assert_uint_eq(0, s_epc);cester_assert_uint_eq(0x555, stat);cester_assert_uint_eq(0x12345678, bcr);cester_assert_uint_eq(0x00800000, madr);cester_assert_uint_eq(0x00000401, chcr);cester_assert_uint_eq(0x84848000, dicr);DICR=0x00008000;dicr=DICR;cester_assert_uint_eq(0x84008000, dicr);DICR=0x00000000;dicr=DICR;cester_assert_uint_eq(0x04000000, dicr);) CESTER_TEST(linked_dma_800001_terminator
 
 cester_assert_uint_eq (0x00800001, madr)
 
 CESTER_TEST (linked_dma_odd_terminator, dma_tests, sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);DPCR=0x00000800;DICR=0x00840000;IMASK=IRQ_VBLANK|IRQ_DMA;uint32_t cmd[2]={ 0, 0xe1000555 };uint32_t terminator=0x00ffffff;cmd[0]=(((uintptr_t)&terminator) &0xffffff)|0x01000001;sendGPUStatus(0x04000002);while((GPU_STATUS &0x10000000)==0);DMA_CTRL[DMA_GPU].MADR=(uintptr_t)&cmd;DMA_CTRL[DMA_GPU].BCR=0x12345678;DMA_CTRL[DMA_GPU].CHCR=0x01000401;unsigned count=0;unsigned timeout=0;while(1) { while((IREG &(IRQ_VBLANK|IRQ_DMA))==0);if(IREG &IRQ_DMA) break;IREG &=~IRQ_VBLANK;if(count++==128) { timeout=1;break;} } IREG=0;uint32_t stat=GPU_STATUS &0x000007ff;uintptr_t bcr=DMA_CTRL[DMA_GPU].BCR;uint32_t madr=DMA_CTRL[DMA_GPU].MADR;uint32_t chcr=DMA_CTRL[DMA_GPU].CHCR;uint32_t dicr=DICR;cester_assert_uint_eq(0, timeout);cester_assert_uint_eq(0, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0, s_from);cester_assert_uint_eq(0, s_epc);cester_assert_uint_eq(0x555, stat);cester_assert_uint_eq(0x12345678, bcr);cester_assert_uint_eq(0x00ffffff, madr);cester_assert_uint_eq(0x00000401, chcr);cester_assert_uint_eq(0x84840000, dicr);dicr &=0xffffff;DICR=dicr|0x04000000;dicr=DICR;cester_assert_uint_eq(0x00840000, dicr);) CESTER_TEST(disabled_dma
 
 cester_assert_uint_eq (0, stat)
 
 cester_assert_uint_eq (0x00010001, bcr)
 
 cester_assert_uint_eq (0x01000201, chcr)
 

Variables

 dma_tests
 
 DPCR = 0x00000800
 
 DICR = 0x00840000
 
 IMASK = IRQ_VBLANK | IRQ_DMA
 
uint32_t cmd = 0xe1000555
 
DMA_CTRL[DMA_GPUMADR = (uintptr_t)&cmd
 
DMA_CTRL[DMA_GPUBCR = 0x00010001
 
DMA_CTRL[DMA_GPUCHCR = 0x01000201
 
unsigned count = 0
 
unsigned timeout = 0
 
 IREG = 0
 
uint32_t stat = GPU_STATUS & 0x000007ff
 
uintptr_t bcr = DMA_CTRL[DMA_GPU].BCR
 
uint32_t madr = DMA_CTRL[DMA_GPU].MADR
 
uint32_t chcr = DMA_CTRL[DMA_GPU].CHCR
 
uint32_t dicr = DICR
 
const uintptr_t expectedAddr = ((uintptr_t)(&cmd + 1)) & 0xffffff
 
uint32_t cmd1 [2] = { 0x01000000, 0x00000000 }
 
uint32_t cmd2 [2] = { 0x01000000, 0x00000000 }
 
uint32_t cmd3 [2] = { 0x01ffffff, 0xe1000555 }
 

Macro Definition Documentation

◆ CESTER_MAYBE_TEST

#define CESTER_MAYBE_TEST   CESTER_TEST

◆ CESTER_NO_SIGNAL

#define CESTER_NO_SIGNAL

◆ CESTER_NO_TIME

#define CESTER_NO_TIME

◆ EXIT_FAILURE

#define EXIT_FAILURE   1

◆ EXIT_SUCCESS

#define EXIT_SUCCESS   0

◆ PCSX_TESTS

#define PCSX_TESTS   0

Function Documentation

◆ cester_assert_uint_eq() [1/25]

cester_assert_uint_eq ( ,
s_epc   
)

◆ cester_assert_uint_eq() [2/25]

cester_assert_uint_eq ( ,
s_from   
)

◆ cester_assert_uint_eq() [3/25]

cester_assert_uint_eq ( ,
s_got40   
)

◆ cester_assert_uint_eq() [4/25]

cester_assert_uint_eq ( ,
s_got80   
)

◆ cester_assert_uint_eq() [5/25]

cester_assert_uint_eq ( ,
stat   
)

◆ cester_assert_uint_eq() [6/25]

cester_assert_uint_eq ( ,
timeout   
)

◆ cester_assert_uint_eq() [7/25]

cester_assert_uint_eq ( 0x00000201  ,
chcr   
)

◆ cester_assert_uint_eq() [8/25]

cester_assert_uint_eq ( 0x00000401  ,
chcr   
)

◆ cester_assert_uint_eq() [9/25]

cester_assert_uint_eq ( 0x00010001  ,
bcr   
)

◆ cester_assert_uint_eq() [10/25]

cester_assert_uint_eq ( 0x00800000  ,
madr   
)

◆ cester_assert_uint_eq() [11/25]

cester_assert_uint_eq ( 0x00800001  ,
madr   
)

◆ cester_assert_uint_eq() [12/25]

cester_assert_uint_eq ( 0x00840000  ,
dicr   
)

◆ cester_assert_uint_eq() [13/25]

cester_assert_uint_eq ( 0x00ffffff  ,
madr   
)

◆ cester_assert_uint_eq() [14/25]

cester_assert_uint_eq ( 0x01000201  ,
chcr   
)

◆ cester_assert_uint_eq() [15/25]

cester_assert_uint_eq ( 0x04000000  ,
dicr   
)

◆ cester_assert_uint_eq() [16/25]

cester_assert_uint_eq ( 0x12345678  ,
bcr   
)

◆ cester_assert_uint_eq() [17/25]

cester_assert_uint_eq ( 0x555  ,
stat   
)

◆ cester_assert_uint_eq() [18/25]

cester_assert_uint_eq ( 0x80848000  ,
dicr   
)

◆ cester_assert_uint_eq() [19/25]

cester_assert_uint_eq ( 0x84008000  ,
dicr   
)

◆ cester_assert_uint_eq() [20/25]

cester_assert_uint_eq ( 0x84800000  ,
dicr   
)

◆ cester_assert_uint_eq() [21/25]

cester_assert_uint_eq ( 0x84840000  ,
dicr   
)

◆ cester_assert_uint_eq() [22/25]

cester_assert_uint_eq ( 0x84848000  ,
dicr   
)

◆ cester_assert_uint_eq() [23/25]

cester_assert_uint_eq ( ,
bcr   
)

◆ cester_assert_uint_eq() [24/25]

cester_assert_uint_eq ( ,
timeout   
)

◆ cester_assert_uint_eq() [25/25]

cester_assert_uint_eq ( expectedAddr  ,
madr   
)

◆ CESTER_TEST() [1/7]

CESTER_TEST ( linked_dma_3_oddlinks  ,
dma_tests  ,
sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);  DPCR = 0x00000800; DICR = 0x00840000; IMASK = IRQ_VBLANK | IRQ_DMAuint32_t cmd1[2] = { 0x01000000, 0x00000000 }; uint32_t cmd2[2] = { 0x01000000, 0x00000000 }; uint32_t cmd3[2] = { 0x01ffffff, 0xe1000555 }; cmd1[0] = (((uint32_t)&cmd2) & 0xffffff) | 0x01000003; cmd2[0] = (((uint32_t)&cmd3) & 0xffffff) | 0x01000003; sendGPUStatus(0x04000002); while ((GPU_STATUS & 0x10000000) == 0); DMA_CTRL[DMA_GPU].MADR = (uintptr_t)&cmd1DMA_CTRL[DMA_GPU].BCR = 0x12345678; DMA_CTRL[DMA_GPU].CHCR = 0x01000401; unsigned count = 0; unsigned timeout = 0; while (1) { while ((IREG & (IRQ_VBLANK | IRQ_DMA)) == 0); if (IREG & IRQ_DMA) break; IREG &= ~IRQ_VBLANKif (count++ == 128) { timeout = 1; break; } } IREG = 0; uint32_t stat = GPU_STATUS & 0x000007ff; uintptr_t bcr = DMA_CTRL[DMA_GPU].BCRuint32_t madr = DMA_CTRL[DMA_GPU].MADRuint32_t chcr = DMA_CTRL[DMA_GPU].CHCRuint32_t dicr = DICRcester_assert_uint_eq(0, timeout); cester_assert_uint_eq(0, s_got40); cester_assert_uint_eq(0, s_got80); cester_assert_uint_eq(0, s_from); cester_assert_uint_eq(0, s_epc); cester_assert_uint_eq(0x555, stat); cester_assert_uint_eq(0x12345678, bcr); cester_assert_uint_eq(0x00ffffff, madr); cester_assert_uint_eq(0x00000401, chcr); cester_assert_uint_eq(0x84840000, dicr); DICR = (dicr & ~0x7f000000) | 0x04000000; dicr = DICRcester_assert_uint_eq(0x00840000, dicr); 
)

◆ CESTER_TEST() [2/7]

CESTER_TEST ( linked_dma_800000_terminator_dicr_toggle  ,
dma_tests  ,
sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);  DPCR = 0x00000800; DICR = 0x00840000; IMASK = IRQ_VBLANK | IRQ_DMAuint32_t cmd[2] = { 0x01800000, 0xe1000555 }; sendGPUStatus(0x04000002); while ((GPU_STATUS & 0x10000000) == 0); DMA_CTRL[DMA_GPU].MADR = (uintptr_t)&cmdDMA_CTRL[DMA_GPU].BCR = 0x12345678; DMA_CTRL[DMA_GPU].CHCR = 0x01000401; unsigned count = 0; unsigned timeout = 0; while (1) { while ((IREG & (IRQ_VBLANK | IRQ_DMA)) == 0); if (IREG & IRQ_DMA) break; IREG &= ~IRQ_VBLANKif (count++ == 128) { timeout = 1; break; } } IREG = 0; uint32_t stat = GPU_STATUS & 0x000007ff; uintptr_t bcr = DMA_CTRL[DMA_GPU].BCRuint32_t madr = DMA_CTRL[DMA_GPU].MADRuint32_t chcr = DMA_CTRL[DMA_GPU].CHCRuint32_t dicr = DICRcester_assert_uint_eq(0, timeout); cester_assert_uint_eq(0, s_got40); cester_assert_uint_eq(0, s_got80); cester_assert_uint_eq(0, s_from); cester_assert_uint_eq(0, s_epc); cester_assert_uint_eq(0x555, stat); cester_assert_uint_eq(0x12345678, bcr); cester_assert_uint_eq(0x00800000, madr); cester_assert_uint_eq(0x00000401, chcr); cester_assert_uint_eq(0x84848000, dicr); DICR = 0x00008000; dicr = DICRcester_assert_uint_eq(0x84008000, dicr); DICR = 0x00000000; dicr = DICRcester_assert_uint_eq(0x04000000, dicr); 
)

◆ CESTER_TEST() [3/7]

CESTER_TEST ( linked_dma_fffff0_terminator  ,
dma_tests  ,
sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);  DPCR = 0x00000800; DICR = 0x00840000; IMASK = IRQ_VBLANK | IRQ_DMAuint32_t cmd[2] = { 0x01fffff0, 0xe1000555 }; sendGPUStatus(0x04000002); while ((GPU_STATUS & 0x10000000) == 0); DMA_CTRL[DMA_GPU].MADR = (uintptr_t)&cmdDMA_CTRL[DMA_GPU].BCR = 0x12345678; DMA_CTRL[DMA_GPU].CHCR = 0x01000401; unsigned count = 0; unsigned timeout = 0; while (1) { while ((IREG & (IRQ_VBLANK | IRQ_DMA)) == 0); if (IREG & IRQ_DMA) break; IREG &= ~IRQ_VBLANKif (count++ == 128) { timeout = 1; break; } } IREG = 0; uint32_t stat = GPU_STATUS & 0x000007ff; uintptr_t bcr = DMA_CTRL[DMA_GPU].BCRuint32_t madr = DMA_CTRL[DMA_GPU].MADRuint32_t chcr = DMA_CTRL[DMA_GPU].CHCRuint32_t dicr = DICRcester_assert_uint_eq(0, timeout); cester_assert_uint_eq(0, s_got40); cester_assert_uint_eq(0, s_got80); cester_assert_uint_eq(0, s_from); cester_assert_uint_eq(0, s_epc); cester_assert_uint_eq(0x555, stat); cester_assert_uint_eq(0x12345678, bcr); cester_assert_uint_eq(0x00fffff0, madr); cester_assert_uint_eq(0x00000401, chcr); cester_assert_uint_eq(0x84848000, dicr); dicr &= 0xffffff; DICR = dicr | 0x04000000; dicr = DICRcester_assert_uint_eq(0x80848000, dicr); dicr &= 0xff7fff; DICR = dicrdicr = DICRcester_assert_uint_eq(0x00840000, dicr); 
)

◆ CESTER_TEST() [4/7]

CESTER_TEST ( linked_dma_odd_terminator  ,
dma_tests  ,
sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);  DPCR = 0x00000800; DICR = 0x00840000; IMASK = IRQ_VBLANK | IRQ_DMAuint32_t cmd[2] = { 0, 0xe1000555 }; uint32_t terminator = 0x00ffffff; cmd[0] = (((uintptr_t)&terminator) & 0xffffff) | 0x01000001; sendGPUStatus(0x04000002); while ((GPU_STATUS & 0x10000000) == 0); DMA_CTRL[DMA_GPU].MADR = (uintptr_t)&cmdDMA_CTRL[DMA_GPU].BCR = 0x12345678; DMA_CTRL[DMA_GPU].CHCR = 0x01000401; unsigned count = 0; unsigned timeout = 0; while (1) { while ((IREG & (IRQ_VBLANK | IRQ_DMA)) == 0); if (IREG & IRQ_DMA) break; IREG &= ~IRQ_VBLANKif (count++ == 128) { timeout = 1; break; } } IREG = 0; uint32_t stat = GPU_STATUS & 0x000007ff; uintptr_t bcr = DMA_CTRL[DMA_GPU].BCRuint32_t madr = DMA_CTRL[DMA_GPU].MADRuint32_t chcr = DMA_CTRL[DMA_GPU].CHCRuint32_t dicr = DICRcester_assert_uint_eq(0, timeout); cester_assert_uint_eq(0, s_got40); cester_assert_uint_eq(0, s_got80); cester_assert_uint_eq(0, s_from); cester_assert_uint_eq(0, s_epc); cester_assert_uint_eq(0x555, stat); cester_assert_uint_eq(0x12345678, bcr); cester_assert_uint_eq(0x00ffffff, madr); cester_assert_uint_eq(0x00000401, chcr); cester_assert_uint_eq(0x84840000, dicr); dicr &= 0xffffff; DICR = dicr | 0x04000000; dicr = DICRcester_assert_uint_eq(0x00840000, dicr); 
)

◆ CESTER_TEST() [5/7]

CESTER_TEST ( normal_dma  ,
dma_tests  ,
sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);  DPCR = 0x00000800; DICR = 0x00840000; IMASK = IRQ_VBLANK | IRQ_DMAuint32_t cmd = 0xe1000555; sendGPUStatus(0x04000002); while ((GPU_STATUS & 0x10000000) == 0); DMA_CTRL[DMA_GPU].MADR = (uintptr_t)&cmdDMA_CTRL[DMA_GPU].BCR = 0x00010001; DMA_CTRL[DMA_GPU].CHCR = 0x01000201; unsigned count = 0; unsigned timeout = 0; while (1) { while ((IREG & (IRQ_VBLANK | IRQ_DMA)) == 0); if (IREG & IRQ_DMA) break; IREG &= ~IRQ_VBLANKif (count++ == 128) { timeout = 1; break; } } IREG = 0; uint32_t stat = GPU_STATUS & 0x000007ff; uintptr_t bcr = DMA_CTRL[DMA_GPU].BCRuint32_t madr = DMA_CTRL[DMA_GPU].MADRuint32_t chcr = DMA_CTRL[DMA_GPU].CHCRuint32_t dicr = DICR; const uintptr_t expectedAddr = ((uintptr_t)(&cmd + 1)) & 0xffffff; cester_assert_uint_eq(0, timeout); cester_assert_uint_eq(0, s_got40); cester_assert_uint_eq(0, s_got80); cester_assert_uint_eq(0, s_from); cester_assert_uint_eq(0, s_epc); cester_assert_uint_eq(0x555, stat); cester_assert_uint_eq(1, bcr); cester_assert_uint_eq(expectedAddrmadr); cester_assert_uint_eq(0x00000201, chcr); cester_assert_uint_eq(0x84840000, dicr); DICR = (dicr & ~0x7f000000) | 0x04000000; dicr = DICRcester_assert_uint_eq(0x00840000, dicr); 
)

◆ CESTER_TEST() [6/7]

CESTER_TEST ( normal_dma_odd_address  ,
dma_tests  ,
sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);  DPCR = 0x00000800; DICR = 0x00840000; IMASK = IRQ_VBLANK | IRQ_DMAuint32_t cmd = 0xe1000555; sendGPUStatus(0x04000002); while ((GPU_STATUS & 0x10000000) == 0); DMA_CTRL[DMA_GPU].MADR = ((uintptr_t)&cmd) | 1; DMA_CTRL[DMA_GPU].BCR = 0x00010001; DMA_CTRL[DMA_GPU].CHCR = 0x01000201; unsigned count = 0; unsigned timeout = 0; while (1) { while ((IREG & (IRQ_VBLANK | IRQ_DMA)) == 0); if (IREG & IRQ_DMA) break; IREG &= ~IRQ_VBLANKif (count++ == 128) { timeout = 1; break; } } IREG = 0; uint32_t stat = GPU_STATUS & 0x000007ff; uintptr_t bcr = DMA_CTRL[DMA_GPU].BCRuint32_t madr = DMA_CTRL[DMA_GPU].MADRuint32_t chcr = DMA_CTRL[DMA_GPU].CHCRuint32_t dicr = DICR; const uintptr_t expectedAddr = ((uintptr_t)(&cmd + 1)) & 0xffffff; cester_assert_uint_eq(0, timeout); cester_assert_uint_eq(0, s_got40); cester_assert_uint_eq(0, s_got80); cester_assert_uint_eq(0, s_from); cester_assert_uint_eq(0, s_epc); cester_assert_uint_eq(0x555, stat); cester_assert_uint_eq(1, bcr); cester_assert_uint_eq(expectedAddrmadr); cester_assert_uint_eq(0x00000201, chcr); cester_assert_uint_eq(0x84840000, dicr); DICR = (dicr & ~0x7f000000) | 0x04000000; dicr = DICRcester_assert_uint_eq(0x00840000, dicr); 
)

◆ CESTER_TEST() [7/7]

CESTER_TEST ( normal_dma_with_3_upper_bits  ,
dma_tests  ,
sendGPUStatus(0);sendGPUStatus(0x04000001);sendGPUData(0xe1000000);  DPCR = 0x00000800; DICR = 0x00840000; IMASK = IRQ_VBLANK | IRQ_DMAuint32_t cmd = 0xe1000555; sendGPUStatus(0x04000002); while ((GPU_STATUS & 0x10000000) == 0); DMA_CTRL[DMA_GPU].MADR = ((uintptr_t)&cmd) | 0xe0000000; DMA_CTRL[DMA_GPU].BCR = 0x00010001; DMA_CTRL[DMA_GPU].CHCR = 0x01000201; unsigned count = 0; unsigned timeout = 0; while (1) { while ((IREG & (IRQ_VBLANK | IRQ_DMA)) == 0); if (IREG & IRQ_DMA) break; IREG &= ~IRQ_VBLANKif (count++ == 128) { timeout = 1; break; } } IREG = 0; uint32_t stat = GPU_STATUS & 0x000007ff; uintptr_t bcr = DMA_CTRL[DMA_GPU].BCRuint32_t madr = DMA_CTRL[DMA_GPU].MADRuint32_t chcr = DMA_CTRL[DMA_GPU].CHCRuint32_t dicr = DICR; const uintptr_t expectedAddr = ((uintptr_t)(&cmd + 1)) & 0xffffff; cester_assert_uint_eq(0, timeout); cester_assert_uint_eq(0, s_got40); cester_assert_uint_eq(0, s_got80); cester_assert_uint_eq(0, s_from); cester_assert_uint_eq(0, s_epc); cester_assert_uint_eq(0x555, stat); cester_assert_uint_eq(1, bcr); cester_assert_uint_eq(expectedAddrmadr); cester_assert_uint_eq(0x00000201, chcr); cester_assert_uint_eq(0x84840000, dicr); DICR = (dicr & ~0x7f000000) | 0x04000000; dicr = DICRcester_assert_uint_eq(0x00840000, dicr); 
)

◆ sendGPUData()

sendGPUData ( 0xe1000000  )

◆ sendGPUStatus() [1/3]

sendGPUStatus ( )

◆ sendGPUStatus() [2/3]

sendGPUStatus ( 0x04000001  )

◆ sendGPUStatus() [3/3]

sendGPUStatus ( 0x04000002  )

◆ while() [1/2]

while ( (GPU_STATUS &0x10000000)  = =0)

◆ while() [2/2]

while ( )

Variable Documentation

◆ BCR

DMA_CTRL [DMA_GPU] BCR = 0x00010001

◆ bcr

uintptr_t bcr = DMA_CTRL[DMA_GPU].BCR

◆ CHCR

DMA_CTRL [DMA_GPU] CHCR = 0x01000201

◆ chcr

◆ cmd

uint32_t cmd = 0xe1000555

◆ cmd1

cmd1[0] = { 0x01000000, 0x00000000 }

◆ cmd2

cmd2[0] = { 0x01000000, 0x00000000 }

◆ cmd3

uint32_t cmd3[2] = { 0x01ffffff, 0xe1000555 }

◆ count

unsigned count = 0

◆ DICR

DICR = 0x00840000

◆ dicr

uint32_t dicr = DICR

◆ dma_tests

dma_tests

◆ DPCR

DPCR = 0x00000800

◆ expectedAddr

const uintptr_t expectedAddr = ((uintptr_t)(&cmd + 1)) & 0xffffff

◆ IMASK

IMASK = IRQ_VBLANK | IRQ_DMA

◆ IREG

IREG = 0

◆ MADR

DMA_CTRL [DMA_GPU] MADR = (uintptr_t)&cmd

◆ madr

◆ stat

uint32_t stat = GPU_STATUS & 0x000007ff

◆ timeout

unsigned timeout = 0