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abr-matrix.c
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1/*
2
3MIT License
4
5Copyright (c) 2026 PCSX-Redux authors
6
7Permission is hereby granted, free of charge, to any person obtaining a copy
8of this software and associated documentation files (the "Software"), to deal
9in the Software without restriction, including without limitation the rights
10to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11copies of the Software, and to permit persons to whom the Software is
12furnished to do so, subject to the following conditions:
13
14The above copyright notice and this permission notice shall be included in all
15copies or substantial portions of the Software.
16
17THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23SOFTWARE.
24
25*/
26
27// ABR mode matrix. The four PS1 semi-trans modes are:
28// ABR=0: B/2 + F/2 (average)
29// ABR=1: B + F (additive, clamp at max)
30// ABR=2: B - F (subtractive, clamp at 0)
31// ABR=3: B + F/4 (add quarter, clamp at max)
32//
33// where B is the existing VRAM pixel ("background") and F is the
34// incoming foreground from the primitive. Per psx-spx the blend runs
35// in 8-bit channel space: VRAM 5-bit B is conceptually shifted up by
36// 3 to form B8, blended with the 8-bit F, then truncated back to 5
37// bits for VRAM. We use 5-bit-boundary-aligned channel values (R5 *
38// 8) so the round-trip is exact and the captured 5-bit output maps
39// cleanly to the documented formulas.
40
42
43// Convenience: build an R-only 24-bit command color from R5 (5-bit
44// value 0..31). Foreground sent to the GPU as 8-bit; we put R8 = R5
45// * 8 in the low byte. G and B are zero so the test focuses on R.
46static inline uint32_t cmdR5(uint8_t r5) {
47 return (uint32_t)(r5 & 0x1f) << 3;
48}
49
50// Pre-fill the test region with an R-only background. b5 is the
51// 5-bit R channel; the rest is zero (which equals 0 in VRAM 5:5:5).
52static inline void fillR(int16_t x, int16_t y, int16_t w, int16_t h,
53 uint8_t b5) {
54 uint16_t pixel = rasterVram555((uint8_t)(b5 & 0x1f), 0, 0);
55 rasterFillRect(x, y, w, h, pixel);
56}
57
58// Draw a 12x12 semi-trans triangle of color F at (0, 0). The
59// triangle is wide enough that probing the deep interior at (4, 4)
60// captures a pixel that's far from the top-left edge artifacts.
61static void drawAbrTri(uint8_t b5, uint8_t f5, uint8_t abr) {
62 rasterReset();
63 fillR(0, 0, 32, 32, b5);
64 rasterSetAbr(abr);
65 rasterFlatTriSemi(cmdR5(f5),
66 0, 0,
67 11, 0,
68 0, 11);
69 rasterFlushPrimitive();
70 rasterSetAbr(0); /* restore default for next test */
71}
72
73static void drawAbrQuad(uint8_t b5, uint8_t f5, uint8_t abr) {
74 rasterReset();
75 fillR(0, 0, 32, 32, b5);
76 rasterSetAbr(abr);
77 rasterFlatQuadSemi(cmdR5(f5),
78 0, 0,
79 11, 0,
80 0, 11,
81 11, 11);
82 rasterFlushPrimitive();
83 rasterSetAbr(0);
84}
85
86static void drawAbrRect(uint8_t b5, uint8_t f5, uint8_t abr) {
87 rasterReset();
88 fillR(0, 0, 32, 32, b5);
89 rasterSetAbr(abr);
90 rasterFlatRectSemi(cmdR5(f5), 0, 0, 12, 12);
91 rasterFlushPrimitive();
92 rasterSetAbr(0);
93}
94
95static void drawAbrLine(uint8_t b5, uint8_t f5, uint8_t abr) {
96 rasterReset();
97 fillR(0, 0, 32, 8, b5);
98 rasterSetAbr(abr);
99 rasterFlatLineSemi(cmdR5(f5), 0, 4, 11, 4);
100 rasterFlushPrimitive();
101 rasterSetAbr(0);
102}
103
104// GP0(0x26) semi-trans textured triangle. The texpage's ABR field
105// would normally drive blend, but tests set E1 ABR explicitly via
106// rasterSetAbr right before the draw - the soft renderer reads ABR
107// from the cached texpage state set most recently via E1 or via the
108// last textured primitive's embedded tpage word.
109static inline void rasterTexTriSemi(uint32_t cmdColor,
110 int16_t x0, int16_t y0, uint8_t u0, uint8_t v0,
111 int16_t x1, int16_t y1, uint8_t u1, uint8_t v1,
112 int16_t x2, int16_t y2, uint8_t u2, uint8_t v2,
113 uint16_t clut_field, uint16_t tpage_field) {
114 waitGPU();
115 GPU_DATA = 0x26000000u | (cmdColor & 0x00ffffffu);
116 GPU_DATA = ((uint32_t)(uint16_t)y0 << 16) | (uint32_t)(uint16_t)x0;
117 GPU_DATA = ((uint32_t)clut_field << 16) |
118 ((uint32_t)v0 << 8) | (uint32_t)u0;
119 GPU_DATA = ((uint32_t)(uint16_t)y1 << 16) | (uint32_t)(uint16_t)x1;
120 GPU_DATA = ((uint32_t)tpage_field << 16) |
121 ((uint32_t)v1 << 8) | (uint32_t)u1;
122 GPU_DATA = ((uint32_t)(uint16_t)y2 << 16) | (uint32_t)(uint16_t)x2;
123 GPU_DATA = (0u << 16) | ((uint32_t)v2 << 8) | (uint32_t)u2;
124}
125
126// Draw a textured semi-trans triangle using the masked CLUT (every
127// entry has bit-15 set). Probe pixel (4, 2) samples texel (4, 2) -
128// 4-bit CLUT entry [4] = vram555(4, 27, 0) | 0x8000.
129static void drawAbrTexTriMasked(uint8_t b5, uint8_t abr) {
130 rasterReset();
131 fillR(0, 0, 32, 16, b5);
132 /* Build texpage with the requested ABR field embedded so the GPU
133 sees the right blend mode even if E1 wasn't re-set. */
134 uint16_t tpage = (uint16_t)((TEX4_TX & 0xf) | ((TEX4_TY & 1) << 4)
135 | ((abr & 3) << 5) | (0u << 7));
136 setTexpage(TEX4_TX, TEX4_TY, 0);
137 rasterSetAbr(abr);
138 setTextureWindow(0, 0, 0, 0);
139 rasterTexTriSemi(TEX_MOD_NEUTRAL,
140 0, 0, 0, 0,
141 11, 0, 11, 0,
142 0, 8, 0, 8,
143 CLUT4_FIELD, tpage);
144 rasterFlushPrimitive();
145 rasterSetAbr(0);
146}
147
148// Semi-trans triangle with E6 SET-MASK enabled. Output should be the
149// blended value with bit-15 OR'd in.
150static void drawAbrTriSetMask(uint8_t b5, uint8_t f5, uint8_t abr) {
151 rasterReset();
152 fillR(0, 0, 32, 32, b5);
153 rasterSetAbr(abr);
154 rasterSetMaskCtrl(1, 0);
155 rasterFlatTriSemi(cmdR5(f5),
156 0, 0, 11, 0, 0, 11);
157 rasterFlushPrimitive();
158 rasterSetMaskCtrl(0, 0);
159 rasterSetAbr(0);
160}
161
162// Semi-trans triangle with E6 CHECK-MASK enabled. Background pre-fill
163// has bit-15 set so the check-mask SKIPS those pixels (no blend
164// applied, sentinel-ish stays).
165static void drawAbrTriCheckMask(uint8_t b5, uint8_t f5, uint8_t abr) {
166 rasterReset();
167 /* Pre-fill with bit-15 already set */
168 uint16_t bg = (uint16_t)(rasterVram555((uint8_t)(b5 & 0x1f), 0, 0) | 0x8000u);
169 rasterFillRect(0, 0, 32, 32, bg);
170 rasterSetAbr(abr);
171 rasterSetMaskCtrl(0, 1);
172 rasterFlatTriSemi(cmdR5(f5),
173 0, 0, 11, 0, 0, 11);
174 rasterFlushPrimitive();
175 rasterSetMaskCtrl(0, 0);
176 rasterSetAbr(0);
177}
178
179) // CESTER_BODY
180
181// ============================================================================
182// ABR_TRI: math sweep across the 4 modes and 9 (B, F) pairs.
183// All probes at (4, 4) - interior of the 12x12 semi-trans tri.
184// B, F values chosen on 5-bit boundaries: 0, 16, 31 (8-bit: 0, 128,
185// 248). 9 pairs cover (0,0), (0,16), (0,31), (16,0), (16,16),
186// (16,31), (31,0), (31,16), (31,31). Each pair tested in all 4 modes
187// = 36 tests.
188// ============================================================================
189
190CESTER_TEST(abr0_tri_b00_f00, gpu_raster_phase12, drawAbrTri(0, 0, 0); ASSERT_PIXEL_EQ(ABR0_B00_F00, 4, 4); )
191CESTER_TEST(abr0_tri_b00_f16, gpu_raster_phase12, drawAbrTri(0, 16, 0); ASSERT_PIXEL_EQ(ABR0_B00_F16, 4, 4); )
192CESTER_TEST(abr0_tri_b00_f31, gpu_raster_phase12, drawAbrTri(0, 31, 0); ASSERT_PIXEL_EQ(ABR0_B00_F31, 4, 4); )
193CESTER_TEST(abr0_tri_b16_f00, gpu_raster_phase12, drawAbrTri(16, 0, 0); ASSERT_PIXEL_EQ(ABR0_B16_F00, 4, 4); )
194CESTER_TEST(abr0_tri_b16_f16, gpu_raster_phase12, drawAbrTri(16, 16, 0); ASSERT_PIXEL_EQ(ABR0_B16_F16, 4, 4); )
195CESTER_TEST(abr0_tri_b16_f31, gpu_raster_phase12, drawAbrTri(16, 31, 0); ASSERT_PIXEL_EQ(ABR0_B16_F31, 4, 4); )
196CESTER_TEST(abr0_tri_b31_f00, gpu_raster_phase12, drawAbrTri(31, 0, 0); ASSERT_PIXEL_EQ(ABR0_B31_F00, 4, 4); )
197CESTER_TEST(abr0_tri_b31_f16, gpu_raster_phase12, drawAbrTri(31, 16, 0); ASSERT_PIXEL_EQ(ABR0_B31_F16, 4, 4); )
198CESTER_TEST(abr0_tri_b31_f31, gpu_raster_phase12, drawAbrTri(31, 31, 0); ASSERT_PIXEL_EQ(ABR0_B31_F31, 4, 4); )
199
200CESTER_TEST(abr1_tri_b00_f00, gpu_raster_phase12, drawAbrTri(0, 0, 1); ASSERT_PIXEL_EQ(ABR1_B00_F00, 4, 4); )
201CESTER_TEST(abr1_tri_b00_f16, gpu_raster_phase12, drawAbrTri(0, 16, 1); ASSERT_PIXEL_EQ(ABR1_B00_F16, 4, 4); )
202CESTER_TEST(abr1_tri_b00_f31, gpu_raster_phase12, drawAbrTri(0, 31, 1); ASSERT_PIXEL_EQ(ABR1_B00_F31, 4, 4); )
203CESTER_TEST(abr1_tri_b16_f00, gpu_raster_phase12, drawAbrTri(16, 0, 1); ASSERT_PIXEL_EQ(ABR1_B16_F00, 4, 4); )
204CESTER_TEST(abr1_tri_b16_f16, gpu_raster_phase12, drawAbrTri(16, 16, 1); ASSERT_PIXEL_EQ(ABR1_B16_F16, 4, 4); )
205CESTER_TEST(abr1_tri_b16_f31, gpu_raster_phase12, drawAbrTri(16, 31, 1); ASSERT_PIXEL_EQ(ABR1_B16_F31, 4, 4); )
206CESTER_TEST(abr1_tri_b31_f00, gpu_raster_phase12, drawAbrTri(31, 0, 1); ASSERT_PIXEL_EQ(ABR1_B31_F00, 4, 4); )
207CESTER_TEST(abr1_tri_b31_f16, gpu_raster_phase12, drawAbrTri(31, 16, 1); ASSERT_PIXEL_EQ(ABR1_B31_F16, 4, 4); )
208CESTER_TEST(abr1_tri_b31_f31, gpu_raster_phase12, drawAbrTri(31, 31, 1); ASSERT_PIXEL_EQ(ABR1_B31_F31, 4, 4); )
209
210CESTER_TEST(abr2_tri_b00_f00, gpu_raster_phase12, drawAbrTri(0, 0, 2); ASSERT_PIXEL_EQ(ABR2_B00_F00, 4, 4); )
211CESTER_TEST(abr2_tri_b00_f16, gpu_raster_phase12, drawAbrTri(0, 16, 2); ASSERT_PIXEL_EQ(ABR2_B00_F16, 4, 4); )
212CESTER_TEST(abr2_tri_b00_f31, gpu_raster_phase12, drawAbrTri(0, 31, 2); ASSERT_PIXEL_EQ(ABR2_B00_F31, 4, 4); )
213CESTER_TEST(abr2_tri_b16_f00, gpu_raster_phase12, drawAbrTri(16, 0, 2); ASSERT_PIXEL_EQ(ABR2_B16_F00, 4, 4); )
214CESTER_TEST(abr2_tri_b16_f16, gpu_raster_phase12, drawAbrTri(16, 16, 2); ASSERT_PIXEL_EQ(ABR2_B16_F16, 4, 4); )
215CESTER_TEST(abr2_tri_b16_f31, gpu_raster_phase12, drawAbrTri(16, 31, 2); ASSERT_PIXEL_EQ(ABR2_B16_F31, 4, 4); )
216CESTER_TEST(abr2_tri_b31_f00, gpu_raster_phase12, drawAbrTri(31, 0, 2); ASSERT_PIXEL_EQ(ABR2_B31_F00, 4, 4); )
217CESTER_TEST(abr2_tri_b31_f16, gpu_raster_phase12, drawAbrTri(31, 16, 2); ASSERT_PIXEL_EQ(ABR2_B31_F16, 4, 4); )
218CESTER_TEST(abr2_tri_b31_f31, gpu_raster_phase12, drawAbrTri(31, 31, 2); ASSERT_PIXEL_EQ(ABR2_B31_F31, 4, 4); )
219
220CESTER_TEST(abr3_tri_b00_f00, gpu_raster_phase12, drawAbrTri(0, 0, 3); ASSERT_PIXEL_EQ(ABR3_B00_F00, 4, 4); )
221CESTER_TEST(abr3_tri_b00_f16, gpu_raster_phase12, drawAbrTri(0, 16, 3); ASSERT_PIXEL_EQ(ABR3_B00_F16, 4, 4); )
222CESTER_TEST(abr3_tri_b00_f31, gpu_raster_phase12, drawAbrTri(0, 31, 3); ASSERT_PIXEL_EQ(ABR3_B00_F31, 4, 4); )
223CESTER_TEST(abr3_tri_b16_f00, gpu_raster_phase12, drawAbrTri(16, 0, 3); ASSERT_PIXEL_EQ(ABR3_B16_F00, 4, 4); )
224CESTER_TEST(abr3_tri_b16_f16, gpu_raster_phase12, drawAbrTri(16, 16, 3); ASSERT_PIXEL_EQ(ABR3_B16_F16, 4, 4); )
225CESTER_TEST(abr3_tri_b16_f31, gpu_raster_phase12, drawAbrTri(16, 31, 3); ASSERT_PIXEL_EQ(ABR3_B16_F31, 4, 4); )
226CESTER_TEST(abr3_tri_b31_f00, gpu_raster_phase12, drawAbrTri(31, 0, 3); ASSERT_PIXEL_EQ(ABR3_B31_F00, 4, 4); )
227CESTER_TEST(abr3_tri_b31_f16, gpu_raster_phase12, drawAbrTri(31, 16, 3); ASSERT_PIXEL_EQ(ABR3_B31_F16, 4, 4); )
228CESTER_TEST(abr3_tri_b31_f31, gpu_raster_phase12, drawAbrTri(31, 31, 3); ASSERT_PIXEL_EQ(ABR3_B31_F31, 4, 4); )
229
230// ============================================================================
231// ABR_PRIM: same blend math across other untextured primitive types.
232// Single representative (B=16, F=16) per ABR mode for each primitive.
233// Confirms primitives share blend math.
234// ============================================================================
235
236CESTER_TEST(abr0_quad_b16_f16, gpu_raster_phase12, drawAbrQuad(16, 16, 0); ASSERT_PIXEL_EQ(ABR0_PRIM_QUAD, 4, 4); )
237CESTER_TEST(abr1_quad_b16_f16, gpu_raster_phase12, drawAbrQuad(16, 16, 1); ASSERT_PIXEL_EQ(ABR1_PRIM_QUAD, 4, 4); )
238CESTER_TEST(abr2_quad_b16_f16, gpu_raster_phase12, drawAbrQuad(16, 16, 2); ASSERT_PIXEL_EQ(ABR2_PRIM_QUAD, 4, 4); )
239CESTER_TEST(abr3_quad_b16_f16, gpu_raster_phase12, drawAbrQuad(16, 16, 3); ASSERT_PIXEL_EQ(ABR3_PRIM_QUAD, 4, 4); )
240
241CESTER_TEST(abr0_rect_b16_f16, gpu_raster_phase12, drawAbrRect(16, 16, 0); ASSERT_PIXEL_EQ(ABR0_PRIM_RECT, 4, 4); )
242CESTER_TEST(abr1_rect_b16_f16, gpu_raster_phase12, drawAbrRect(16, 16, 1); ASSERT_PIXEL_EQ(ABR1_PRIM_RECT, 4, 4); )
243CESTER_TEST(abr2_rect_b16_f16, gpu_raster_phase12, drawAbrRect(16, 16, 2); ASSERT_PIXEL_EQ(ABR2_PRIM_RECT, 4, 4); )
244CESTER_TEST(abr3_rect_b16_f16, gpu_raster_phase12, drawAbrRect(16, 16, 3); ASSERT_PIXEL_EQ(ABR3_PRIM_RECT, 4, 4); )
245
246CESTER_TEST(abr0_line_b16_f16, gpu_raster_phase12, drawAbrLine(16, 16, 0); ASSERT_PIXEL_EQ(ABR0_PRIM_LINE, 5, 4); )
247CESTER_TEST(abr1_line_b16_f16, gpu_raster_phase12, drawAbrLine(16, 16, 1); ASSERT_PIXEL_EQ(ABR1_PRIM_LINE, 5, 4); )
248CESTER_TEST(abr2_line_b16_f16, gpu_raster_phase12, drawAbrLine(16, 16, 2); ASSERT_PIXEL_EQ(ABR2_PRIM_LINE, 5, 4); )
249CESTER_TEST(abr3_line_b16_f16, gpu_raster_phase12, drawAbrLine(16, 16, 3); ASSERT_PIXEL_EQ(ABR3_PRIM_LINE, 5, 4); )
250
251// ============================================================================
252// ABR_TEX_MASKED: textured semi-trans tri at 4-bit with masked CLUT.
253// CLUT entry [4] has bit-15 set so the semi-trans gate fires. Probe
254// (4, 2) which samples texel u=4, CLUT[4] = vram555(4, 27, 0)|0x8000.
255// Then blend formula applies. Capture for all 4 ABR modes.
256// ============================================================================
257
258CESTER_TEST(abr0_tex_masked_b16, gpu_raster_phase12, drawAbrTexTriMasked(16, 0); ASSERT_PIXEL_EQ(ABR0_TEX_MASKED, 4, 2); )
259CESTER_TEST(abr1_tex_masked_b16, gpu_raster_phase12, drawAbrTexTriMasked(16, 1); ASSERT_PIXEL_EQ(ABR1_TEX_MASKED, 4, 2); )
260CESTER_TEST(abr2_tex_masked_b16, gpu_raster_phase12, drawAbrTexTriMasked(16, 2); ASSERT_PIXEL_EQ(ABR2_TEX_MASKED, 4, 2); )
261CESTER_TEST(abr3_tex_masked_b16, gpu_raster_phase12, drawAbrTexTriMasked(16, 3); ASSERT_PIXEL_EQ(ABR3_TEX_MASKED, 4, 2); )
262
263// ============================================================================
264// ABR_MASKBIT: set-mask and check-mask interactions.
265// Set-mask: output should be blended value with bit-15 forced to 1.
266// Check-mask: pre-fill has bit-15 set, so writes are SKIPPED - read
267// returns the pre-fill value unchanged.
268// ============================================================================
269
270CESTER_TEST(abr0_setmask_b16_f16, gpu_raster_phase12, drawAbrTriSetMask(16, 16, 0); ASSERT_PIXEL_EQ(ABR0_SETMASK, 4, 4); )
271CESTER_TEST(abr1_setmask_b16_f16, gpu_raster_phase12, drawAbrTriSetMask(16, 16, 1); ASSERT_PIXEL_EQ(ABR1_SETMASK, 4, 4); )
272CESTER_TEST(abr2_setmask_b16_f16, gpu_raster_phase12, drawAbrTriSetMask(16, 16, 2); ASSERT_PIXEL_EQ(ABR2_SETMASK, 4, 4); )
273CESTER_TEST(abr3_setmask_b16_f16, gpu_raster_phase12, drawAbrTriSetMask(16, 16, 3); ASSERT_PIXEL_EQ(ABR3_SETMASK, 4, 4); )
274
275CESTER_TEST(abr0_checkmask_b16_f16, gpu_raster_phase12, drawAbrTriCheckMask(16, 16, 0); ASSERT_PIXEL_EQ(ABR0_CHECKMASK, 4, 4); )
276CESTER_TEST(abr1_checkmask_b16_f16, gpu_raster_phase12, drawAbrTriCheckMask(16, 16, 1); ASSERT_PIXEL_EQ(ABR1_CHECKMASK, 4, 4); )
277CESTER_TEST(abr2_checkmask_b16_f16, gpu_raster_phase12, drawAbrTriCheckMask(16, 16, 2); ASSERT_PIXEL_EQ(ABR2_CHECKMASK, 4, 4); )
278CESTER_TEST(abr3_checkmask_b16_f16, gpu_raster_phase12, drawAbrTriCheckMask(16, 16, 3); ASSERT_PIXEL_EQ(ABR3_CHECKMASK, 4, 4); )
CESTER_BODY(static int s_got40;static int s_got80;static uint32_t s_cause;static uint32_t s_epc;static uint32_t s_from;static uint32_t *s_resume;static uint32_t *s_regs;static uint32_t(*s_customhandler)()=NULL;static uint32_t s_oldIMASK;static uint32_t s_oldDPCR;static uint32_t s_oldDICR;uint32_t handler(uint32_t *regs, uint32_t from) { if(from==0x40) s_got40=1;if(from==0x80) s_got80=1;uint32_t cause;uint32_t epc;s_from=from;asm("mfc0 %0, $13\nnop\nmfc0 %1, $14\nnop" :"=r"(cause), "=r"(epc));s_cause=cause;s_epc=epc;if(s_customhandler) { return s_customhandler();} else { return s_resume ?((uint32_t) s_resume) :(epc+4);} } void installExceptionHandlers(uint32_t(*handler)(uint32_t *regs, uint32_t from));void uninstallExceptionHandlers();uint32_t branchbranch1();uint32_t branchbranch2();uint32_t jumpjump1();uint32_t jumpjump2();uint32_t cpu_LWR_LWL_half(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_nodelay(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_delayed(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_load_different(uint32_t buff[], uint32_t initial);uint32_t cpu_LW_LWR(uint32_t buff[], uint32_t initial);uint32_t cpu_delayed_load(uint32_t buff[], uint32_t override);uint32_t cpu_delayed_load_cancelled(uint32_t buff[], uint32_t override);uint64_t cpu_delayed_load_load(uint32_t buff[], uint32_t override);uint32_t linkandload();uint32_t lwandlink();uint32_t nolink();static int s_interruptsWereEnabled;) CESTER_BEFORE_EACH(cpu_tests
CESTER_TEST(cpu_cop0_basic_write_bp, cpu_tests, uint32_t expectedEPC;uint32_t t;volatile uint32_t *ptr=(volatile uint32_t *) 0x58; *ptr=1;__asm__ volatile("" " lui %0, 0b1100101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0xfffffff0\n" " mtc0 %0, $9\n" :"=r"(t));cester_assert_uint_eq(1, *ptr);__asm__ volatile("la %0, 1f\n1:\nsw $0, 0x58($0)" :"=r"(expectedEPC));__asm__ volatile("mtc0 $0, $7\n");cester_assert_uint_eq(0, *ptr);cester_assert_uint_eq(1, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0x40, s_from);cester_assert_uint_eq(expectedEPC, s_epc);) CESTER_TEST(cpu_cop0_kseg_write_bp
#define GPU_DATA
Definition hwregs.h:52
#define ABR0_PRIM_LINE
Definition raster-expected-phase12.h:118
#define ABR3_B16_F31
Definition raster-expected-phase12.h:99
#define ABR1_B16_F16
Definition raster-expected-phase12.h:70
#define ABR2_TEX_MASKED
Definition raster-expected-phase12.h:153
#define ABR0_B16_F31
Definition raster-expected-phase12.h:57
#define ABR3_SETMASK
Definition raster-expected-phase12.h:164
#define ABR1_B16_F00
Definition raster-expected-phase12.h:69
#define ABR3_PRIM_LINE
Definition raster-expected-phase12.h:121
#define ABR0_PRIM_QUAD
Definition raster-expected-phase12.h:108
#define ABR2_B00_F00
Definition raster-expected-phase12.h:80
#define ABR2_B00_F31
Definition raster-expected-phase12.h:82
#define ABR1_SETMASK
Definition raster-expected-phase12.h:162
#define ABR0_B00_F16
Definition raster-expected-phase12.h:53
#define ABR0_B16_F16
Definition raster-expected-phase12.h:56
#define ABR0_B31_F31
Definition raster-expected-phase12.h:60
#define ABR1_B16_F31
Definition raster-expected-phase12.h:71
#define ABR1_B00_F00
Definition raster-expected-phase12.h:66
#define ABR0_B16_F00
Definition raster-expected-phase12.h:55
#define ABR3_CHECKMASK
Definition raster-expected-phase12.h:174
#define ABR1_PRIM_LINE
Definition raster-expected-phase12.h:119
#define ABR2_PRIM_LINE
Definition raster-expected-phase12.h:120
#define ABR1_B31_F31
Definition raster-expected-phase12.h:74
#define ABR3_TEX_MASKED
Definition raster-expected-phase12.h:154
#define ABR0_B31_F16
Definition raster-expected-phase12.h:59
#define ABR3_B16_F16
Definition raster-expected-phase12.h:98
#define ABR2_B31_F16
Definition raster-expected-phase12.h:87
#define ABR0_PRIM_RECT
Definition raster-expected-phase12.h:113
#define ABR3_B00_F00
Definition raster-expected-phase12.h:94
#define ABR3_B31_F31
Definition raster-expected-phase12.h:102
#define ABR2_B16_F31
Definition raster-expected-phase12.h:85
#define ABR3_B00_F16
Definition raster-expected-phase12.h:95
#define ABR2_B31_F31
Definition raster-expected-phase12.h:88
#define ABR3_B31_F16
Definition raster-expected-phase12.h:101
#define ABR0_B00_F00
Definition raster-expected-phase12.h:52
#define ABR2_CHECKMASK
Definition raster-expected-phase12.h:173
#define ABR1_B00_F16
Definition raster-expected-phase12.h:67
#define ABR0_B00_F31
Definition raster-expected-phase12.h:54
#define ABR1_PRIM_QUAD
Definition raster-expected-phase12.h:109
#define ABR3_PRIM_RECT
Definition raster-expected-phase12.h:116
#define ABR0_CHECKMASK
Definition raster-expected-phase12.h:171
#define ABR2_B16_F00
Definition raster-expected-phase12.h:83
#define ABR2_B00_F16
Definition raster-expected-phase12.h:81
#define ABR2_B31_F00
Definition raster-expected-phase12.h:86
#define ABR2_B16_F16
Definition raster-expected-phase12.h:84
#define ABR3_B31_F00
Definition raster-expected-phase12.h:100
#define ABR3_B16_F00
Definition raster-expected-phase12.h:97
#define ABR1_B31_F16
Definition raster-expected-phase12.h:73
#define ABR1_CHECKMASK
Definition raster-expected-phase12.h:172
#define ABR1_B00_F31
Definition raster-expected-phase12.h:68
#define ABR2_PRIM_QUAD
Definition raster-expected-phase12.h:110
#define ABR0_B31_F00
Definition raster-expected-phase12.h:58
#define ABR0_SETMASK
Definition raster-expected-phase12.h:161
#define ABR2_SETMASK
Definition raster-expected-phase12.h:163
#define ABR1_PRIM_RECT
Definition raster-expected-phase12.h:114
#define ABR3_PRIM_QUAD
Definition raster-expected-phase12.h:111
#define ABR3_B00_F31
Definition raster-expected-phase12.h:96
#define ABR1_TEX_MASKED
Definition raster-expected-phase12.h:152
#define ABR0_TEX_MASKED
Definition raster-expected-phase12.h:151
#define ABR2_PRIM_RECT
Definition raster-expected-phase12.h:115
#define ABR1_B31_F00
Definition raster-expected-phase12.h:72
#define ASSERT_PIXEL_EQ(expected, x_, y_)
Definition raster-helpers.h:472
void uint32_t(classId, spec)
#define CLUT4_FIELD
Definition texture-fixtures.h:83
#define TEX_MOD_NEUTRAL
Definition texture-fixtures.h:328
#define TEX4_TY
Definition texture-fixtures.h:56
#define TEX4_TX
Definition texture-fixtures.h:55
uint16_t v2
Definition timers.c:262
uint16_t v1
Definition timers.c:260