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raster-expected.h File Reference
#include "raster-helpers.h"
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Macros

#define EXPECT_TRI_A_PIXEL_0_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 top-left corner */
 
#define EXPECT_TRI_A_PIXEL_1_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 top edge inclusive */
 
#define EXPECT_TRI_A_PIXEL_2_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_A_PIXEL_3_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 last-included pixel */
 
#define EXPECT_TRI_A_PIXEL_4_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge excluded */
 
#define EXPECT_TRI_A_PIXEL_0_1   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_A_PIXEL_2_1   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_A_PIXEL_3_1   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 hypotenuse boundary y=1 x=3 */
 
#define EXPECT_TRI_A_PIXEL_1_2   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_A_PIXEL_2_2   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 hypotenuse boundary y=2 x=2 */
 
#define EXPECT_TRI_A_PIXEL_0_3   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 bottom row, single pixel */
 
#define EXPECT_TRI_A_PIXEL_1_3   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 hypotenuse boundary y=3 x=1 */
 
#define EXPECT_TRI_A_PIXEL_0_4   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom edge excluded */
 
#define EXPECT_TRI_B_PIXEL_0_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 1px triangle, single inclusive pixel */
 
#define EXPECT_TRI_B_PIXEL_1_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_B_PIXEL_0_1   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_B_PIXEL_1_1   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_C_PIXEL_1019_507   RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_C_PIXEL_1020_507   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_C_PIXEL_1019_508   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_C_PIXEL_1020_508   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_D_PIXEL_0_0   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_D_PIXEL_3_0   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_D_PIXEL_4_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 top-right corner: right edge excludes */
 
#define EXPECT_TRI_D_PIXEL_0_1   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 left of diagonal */
 
#define EXPECT_TRI_D_PIXEL_1_1   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_D_PIXEL_3_1   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 last interior x */
 
#define EXPECT_TRI_D_PIXEL_4_1   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge */
 
#define EXPECT_TRI_D_PIXEL_3_3   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 bottom-right interior pixel */
 
#define EXPECT_TRI_D_PIXEL_4_4   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_E_PIXEL_0_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 top-left of top edge */
 
#define EXPECT_TRI_E_PIXEL_3_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 right end of top edge */
 
#define EXPECT_TRI_E_PIXEL_4_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right-vertex of top edge */
 
#define EXPECT_TRI_E_PIXEL_1_1   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_E_PIXEL_3_1   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_E_PIXEL_2_2   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_E_PIXEL_2_3   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_E_PIXEL_2_4   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 apex - bottom convention */
 
#define EXPECT_TRI_F_PIXEL_0_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 collinear: no fill */
 
#define EXPECT_TRI_F_PIXEL_2_2   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 collinear: no fill */
 
#define EXPECT_TRI_F_PIXEL_4_4   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 collinear: no fill */
 
#define EXPECT_TRI_F_PIXEL_1_1   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_G_PIXEL_0_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_G_PIXEL_5_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_G_PIXEL_10_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_H_PIXEL_0_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_H_PIXEL_0_5   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_H_PIXEL_0_10   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_I_PIXEL_0_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15: dropped */
 
#define EXPECT_TRI_I_PIXEL_1_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_I_PIXEL_0_1   RASTER_VRAM_WHITE /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_I_PIXEL_1_1   RASTER_VRAM_WHITE /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_TRI_I_PIXEL_0_2   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15: bottom edge excluded */
 
#define EXPECT_QUAD_Q_PIXEL_0_0   RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_QUAD_Q_PIXEL_3_0   RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 last x on top edge */
 
#define EXPECT_QUAD_Q_PIXEL_4_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge */
 
#define EXPECT_QUAD_Q_PIXEL_0_3   RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_QUAD_Q_PIXEL_3_3   RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 interior corner */
 
#define EXPECT_QUAD_Q_PIXEL_4_4   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom-right corner outside */
 
#define EXPECT_QUAD_Q_PIXEL_0_4   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom edge */
 
#define EXPECT_QUAD_Q_PIXEL_2_2   RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 center, on diagonal seam */
 
#define EXPECT_RECT_R1_PIXEL_10_10   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_RECT_R1_PIXEL_13_13   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 last interior pixel */
 
#define EXPECT_RECT_R1_PIXEL_14_10   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge */
 
#define EXPECT_RECT_R1_PIXEL_10_14   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom edge */
 
#define EXPECT_RECT_R1_PIXEL_9_10   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 before left edge */
 
#define EXPECT_RECT_R2_PIXEL_0_0   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 clipped-to-draw-area */
 
#define EXPECT_RECT_R2_PIXEL_5_5   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 last interior pixel */
 
#define EXPECT_RECT_R2_PIXEL_6_5   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 past rect */
 
#define EXPECT_OFFSET_PIXEL_50_50   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_OFFSET_PIXEL_53_50   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_OFFSET_PIXEL_54_50   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_OFFSET_PIXEL_50_54   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */
 
#define EXPECT_OFFSET_PIXEL_0_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 original origin untouched */
 

Macro Definition Documentation

◆ EXPECT_OFFSET_PIXEL_0_0

#define EXPECT_OFFSET_PIXEL_0_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 original origin untouched */

◆ EXPECT_OFFSET_PIXEL_50_50

#define EXPECT_OFFSET_PIXEL_50_50   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_OFFSET_PIXEL_50_54

#define EXPECT_OFFSET_PIXEL_50_54   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_OFFSET_PIXEL_53_50

#define EXPECT_OFFSET_PIXEL_53_50   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_OFFSET_PIXEL_54_50

#define EXPECT_OFFSET_PIXEL_54_50   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_QUAD_Q_PIXEL_0_0

#define EXPECT_QUAD_Q_PIXEL_0_0   RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_QUAD_Q_PIXEL_0_3

#define EXPECT_QUAD_Q_PIXEL_0_3   RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_QUAD_Q_PIXEL_0_4

#define EXPECT_QUAD_Q_PIXEL_0_4   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom edge */

◆ EXPECT_QUAD_Q_PIXEL_2_2

#define EXPECT_QUAD_Q_PIXEL_2_2   RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 center, on diagonal seam */

◆ EXPECT_QUAD_Q_PIXEL_3_0

#define EXPECT_QUAD_Q_PIXEL_3_0   RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 last x on top edge */

◆ EXPECT_QUAD_Q_PIXEL_3_3

#define EXPECT_QUAD_Q_PIXEL_3_3   RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 interior corner */

◆ EXPECT_QUAD_Q_PIXEL_4_0

#define EXPECT_QUAD_Q_PIXEL_4_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge */

◆ EXPECT_QUAD_Q_PIXEL_4_4

#define EXPECT_QUAD_Q_PIXEL_4_4   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom-right corner outside */

◆ EXPECT_RECT_R1_PIXEL_10_10

#define EXPECT_RECT_R1_PIXEL_10_10   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_RECT_R1_PIXEL_10_14

#define EXPECT_RECT_R1_PIXEL_10_14   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom edge */

◆ EXPECT_RECT_R1_PIXEL_13_13

#define EXPECT_RECT_R1_PIXEL_13_13   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 last interior pixel */

◆ EXPECT_RECT_R1_PIXEL_14_10

#define EXPECT_RECT_R1_PIXEL_14_10   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge */

◆ EXPECT_RECT_R1_PIXEL_9_10

#define EXPECT_RECT_R1_PIXEL_9_10   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 before left edge */

◆ EXPECT_RECT_R2_PIXEL_0_0

#define EXPECT_RECT_R2_PIXEL_0_0   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 clipped-to-draw-area */

◆ EXPECT_RECT_R2_PIXEL_5_5

#define EXPECT_RECT_R2_PIXEL_5_5   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 last interior pixel */

◆ EXPECT_RECT_R2_PIXEL_6_5

#define EXPECT_RECT_R2_PIXEL_6_5   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 past rect */

◆ EXPECT_TRI_A_PIXEL_0_0

#define EXPECT_TRI_A_PIXEL_0_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 top-left corner */

◆ EXPECT_TRI_A_PIXEL_0_1

#define EXPECT_TRI_A_PIXEL_0_1   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_A_PIXEL_0_3

#define EXPECT_TRI_A_PIXEL_0_3   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 bottom row, single pixel */

◆ EXPECT_TRI_A_PIXEL_0_4

#define EXPECT_TRI_A_PIXEL_0_4   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 bottom edge excluded */

◆ EXPECT_TRI_A_PIXEL_1_0

#define EXPECT_TRI_A_PIXEL_1_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 top edge inclusive */

◆ EXPECT_TRI_A_PIXEL_1_2

#define EXPECT_TRI_A_PIXEL_1_2   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_A_PIXEL_1_3

#define EXPECT_TRI_A_PIXEL_1_3   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 hypotenuse boundary y=3 x=1 */

◆ EXPECT_TRI_A_PIXEL_2_0

#define EXPECT_TRI_A_PIXEL_2_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_A_PIXEL_2_1

#define EXPECT_TRI_A_PIXEL_2_1   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_A_PIXEL_2_2

#define EXPECT_TRI_A_PIXEL_2_2   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 hypotenuse boundary y=2 x=2 */

◆ EXPECT_TRI_A_PIXEL_3_0

#define EXPECT_TRI_A_PIXEL_3_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 last-included pixel */

◆ EXPECT_TRI_A_PIXEL_3_1

#define EXPECT_TRI_A_PIXEL_3_1   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 hypotenuse boundary y=1 x=3 */

◆ EXPECT_TRI_A_PIXEL_4_0

#define EXPECT_TRI_A_PIXEL_4_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge excluded */

◆ EXPECT_TRI_B_PIXEL_0_0

#define EXPECT_TRI_B_PIXEL_0_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 1px triangle, single inclusive pixel */

◆ EXPECT_TRI_B_PIXEL_0_1

#define EXPECT_TRI_B_PIXEL_0_1   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_B_PIXEL_1_0

#define EXPECT_TRI_B_PIXEL_1_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_B_PIXEL_1_1

#define EXPECT_TRI_B_PIXEL_1_1   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_C_PIXEL_1019_507

#define EXPECT_TRI_C_PIXEL_1019_507   RASTER_VRAM_BLUE /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_C_PIXEL_1019_508

#define EXPECT_TRI_C_PIXEL_1019_508   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_C_PIXEL_1020_507

#define EXPECT_TRI_C_PIXEL_1020_507   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_C_PIXEL_1020_508

#define EXPECT_TRI_C_PIXEL_1020_508   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_D_PIXEL_0_0

#define EXPECT_TRI_D_PIXEL_0_0   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_D_PIXEL_0_1

#define EXPECT_TRI_D_PIXEL_0_1   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 left of diagonal */

◆ EXPECT_TRI_D_PIXEL_1_1

#define EXPECT_TRI_D_PIXEL_1_1   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_D_PIXEL_3_0

#define EXPECT_TRI_D_PIXEL_3_0   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_D_PIXEL_3_1

#define EXPECT_TRI_D_PIXEL_3_1   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 last interior x */

◆ EXPECT_TRI_D_PIXEL_3_3

#define EXPECT_TRI_D_PIXEL_3_3   RASTER_VRAM_GREEN /* HW_VERIFIED 2026-05-15 bottom-right interior pixel */

◆ EXPECT_TRI_D_PIXEL_4_0

#define EXPECT_TRI_D_PIXEL_4_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 top-right corner: right edge excludes */

◆ EXPECT_TRI_D_PIXEL_4_1

#define EXPECT_TRI_D_PIXEL_4_1   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right edge */

◆ EXPECT_TRI_D_PIXEL_4_4

#define EXPECT_TRI_D_PIXEL_4_4   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_E_PIXEL_0_0

#define EXPECT_TRI_E_PIXEL_0_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 top-left of top edge */

◆ EXPECT_TRI_E_PIXEL_1_1

#define EXPECT_TRI_E_PIXEL_1_1   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_E_PIXEL_2_2

#define EXPECT_TRI_E_PIXEL_2_2   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_E_PIXEL_2_3

#define EXPECT_TRI_E_PIXEL_2_3   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_E_PIXEL_2_4

#define EXPECT_TRI_E_PIXEL_2_4   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 apex - bottom convention */

◆ EXPECT_TRI_E_PIXEL_3_0

#define EXPECT_TRI_E_PIXEL_3_0   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 right end of top edge */

◆ EXPECT_TRI_E_PIXEL_3_1

#define EXPECT_TRI_E_PIXEL_3_1   RASTER_VRAM_RED /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_E_PIXEL_4_0

#define EXPECT_TRI_E_PIXEL_4_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 right-vertex of top edge */

◆ EXPECT_TRI_F_PIXEL_0_0

#define EXPECT_TRI_F_PIXEL_0_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 collinear: no fill */

◆ EXPECT_TRI_F_PIXEL_1_1

#define EXPECT_TRI_F_PIXEL_1_1   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_F_PIXEL_2_2

#define EXPECT_TRI_F_PIXEL_2_2   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 collinear: no fill */

◆ EXPECT_TRI_F_PIXEL_4_4

#define EXPECT_TRI_F_PIXEL_4_4   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 collinear: no fill */

◆ EXPECT_TRI_G_PIXEL_0_0

#define EXPECT_TRI_G_PIXEL_0_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_G_PIXEL_10_0

#define EXPECT_TRI_G_PIXEL_10_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_G_PIXEL_5_0

#define EXPECT_TRI_G_PIXEL_5_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_H_PIXEL_0_0

#define EXPECT_TRI_H_PIXEL_0_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_H_PIXEL_0_10

#define EXPECT_TRI_H_PIXEL_0_10   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_H_PIXEL_0_5

#define EXPECT_TRI_H_PIXEL_0_5   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_I_PIXEL_0_0

#define EXPECT_TRI_I_PIXEL_0_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15: dropped */

◆ EXPECT_TRI_I_PIXEL_0_1

#define EXPECT_TRI_I_PIXEL_0_1   RASTER_VRAM_WHITE /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_I_PIXEL_0_2

#define EXPECT_TRI_I_PIXEL_0_2   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15: bottom edge excluded */

◆ EXPECT_TRI_I_PIXEL_1_0

#define EXPECT_TRI_I_PIXEL_1_0   RASTER_SENTINEL /* HW_VERIFIED 2026-05-15 */

◆ EXPECT_TRI_I_PIXEL_1_1

#define EXPECT_TRI_I_PIXEL_1_1   RASTER_VRAM_WHITE /* HW_VERIFIED 2026-05-15 */