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Nugget
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Go to the source code of this file.
Functions | |
| CESTER_TEST (prec_mac1_positive_overflow, gte_tests, cop2_putc(0, 0x00007fff);cop2_putc(1, 0x00000000);cop2_putc(2, 0x00000000);cop2_putc(3, 0x00000000);cop2_putc(4, 0);cop2_putc(5, 0x7fffffff);cop2_putc(6, 0);cop2_putc(7, 0);cop2_put(0,(0<< 16)|0x7fff);cop2_put(1, 0);gte_clear_flag();cop2_cmd(COP2_MVMVA(0, COP2_MX_RT, COP2_V_V0, COP2_CV_TR, 0));uint32_t flag=gte_read_flag();uint32_t f30=(flag > > 30) &1;ramsyscall_printf("MAC1 pos overflow: FLAG=0x%08x F30=%u\n", flag, f30);cester_assert_uint_eq(1, f30);) CESTER_TEST(prec_mac1_negative_overflow | |
| cop2_putc (0, 0x00007fff) | |
| cop2_putc (1, 0x00000000) | |
| cop2_putc (2, 0x00000000) | |
| cop2_putc (3, 0x00000000) | |
| cop2_putc (4, 0) | |
| cop2_putc (5, 0x80000000) | |
| cop2_putc (6, 0) | |
| cop2_putc (7, 0) | |
| cop2_put (0,(0<< 16)|0x8000) | |
| cop2_put (1, 0) | |
| gte_clear_flag () | |
| cop2_cmd (COP2_MVMVA(0, COP2_MX_RT, COP2_V_V0, COP2_CV_TR, 0)) | |
| ramsyscall_printf ("MAC1 neg overflow: FLAG=0x%08x F27=%u\n", flag, f27) | |
| cester_assert_uint_eq (1, f27) | |
| CESTER_TEST (prec_mac2_overflow, gte_tests, cop2_putc(0, 0x00000000);cop2_putc(1, 0x7fff0000);cop2_putc(2, 0x00000000);cop2_putc(3, 0x00000000);cop2_putc(4, 0);cop2_putc(5, 0);cop2_putc(6, 0x7fffffff);cop2_putc(7, 0);cop2_put(0,(0<< 16)|0x7fff);cop2_put(1, 0);gte_clear_flag();cop2_cmd(COP2_MVMVA(0, COP2_MX_RT, COP2_V_V0, COP2_CV_TR, 0));uint32_t flag=gte_read_flag();uint32_t f29=(flag > > 29) &1;ramsyscall_printf("MAC2 pos overflow: FLAG=0x%08x F29=%u\n", flag, f29);cester_assert_uint_eq(1, f29);) CESTER_TEST(prec_mac3_overflow | |
| cop2_putc (0, 0x00000000) | |
| cop2_putc (3, 0x00007fff) | |
| cop2_putc (5, 0) | |
| cop2_putc (7, 0x7fffffff) | |
| cester_assert_uint_eq (1, f28) | |
| CESTER_TEST (prec_mac_double_overflow, gte_tests, cop2_putc(0, 0x00000000);cop2_putc(2, 0x00007fff);cop2_putc(4, 0x7fff);cop2_put(9, 0);cop2_put(10, 0x7fff);cop2_put(11, 0x7fff);gte_clear_flag();cop2_cmd(COP2_OP_CP(0, 0));int32_t mac1;uint32_t flag;cop2_get(25, mac1);flag=gte_read_flag();ramsyscall_printf("double overflow: MAC1=%d FLAG=0x%08x\n", mac1, flag);cester_assert_int_eq(0, mac1);cester_assert_uint_eq(0, flag);) CESTER_TEST(prec_div_1_over_1 | |
| gte_set_identity_rotation () | |
| gte_set_translation (0, 0, 0) | |
| cop2_putc (24, 0) | |
| cop2_putc (25, 0) | |
| cop2_putc (26, 1) | |
| cop2_putc (27, 0) | |
| cop2_putc (28, 0) | |
| cop2_put (1, 1) | |
| cop2_cmd (COP2_RTPS(1, 0)) | |
| cop2_get (14, sxy2) | |
| cester_assert_uint_eq (0, f17) | |
| CESTER_TEST (prec_div_100_over_1000, gte_tests, gte_set_identity_rotation();gte_set_translation(0, 0, 0);cop2_putc(24, 0);cop2_putc(25, 0);cop2_putc(26, 100);cop2_putc(27, 0);cop2_putc(28, 0);cop2_put(0,(0<< 16)|1000);cop2_put(1, 1000);gte_clear_flag();cop2_cmd(COP2_RTPS(1, 0));uint32_t sxy2;cop2_get(14, sxy2);int16_t sx=(int16_t)(sxy2 &0xffff);ramsyscall_printf("div 100/1000: SX=%d\n", sx);cester_assert_int_eq(100, sx);) CESTER_TEST(prec_div_corner_f015_780b | |
| cop2_putc (26, 0xf015) | |
| cop2_put (1, 0x780b) | |
| CESTER_TEST (prec_div_large_h, gte_tests, gte_set_identity_rotation();gte_set_translation(0, 0, 0);cop2_putc(24, 0);cop2_putc(25, 0);cop2_putc(26, 0xfffe);cop2_putc(27, 0);cop2_putc(28, 0);cop2_put(0,(0<< 16)|1);cop2_put(1, 0x7fff);gte_clear_flag();cop2_cmd(COP2_RTPS(1, 0));uint32_t flag;flag=gte_read_flag();uint32_t f17=(flag > > 17) &1;ramsyscall_printf("div large H: FLAG=0x%08x F17=%u\n", flag, f17);cester_assert_uint_eq(1, f17);) CESTER_TEST(prec_div_sz3_one | |
| cop2_get (9, ir1) | |
| cester_assert_int_eq (1, sx) | |
| CESTER_TEST (prec_rtps_sf0_ir3_flag_anomaly, gte_tests, gte_set_identity_rotation();cop2_putc(5, 0);cop2_putc(6, 0);cop2_putc(7, 0);cop2_putc(24, 0);cop2_putc(25, 0);cop2_putc(26, 200);cop2_putc(27, 0);cop2_putc(28, 0);cop2_put(0, 0x00000000);cop2_put(1, 8);gte_clear_flag();cop2_cmd(COP2_RTPS(0, 0));int32_t mac3;uint32_t ir3, flag;cop2_get(27, mac3);cop2_get(11, ir3);flag=gte_read_flag();uint32_t f22=(flag > > 22) &1;ramsyscall_printf("sf=0 anomaly: MAC3=%d IR3=0x%04x FLAG=0x%08x F22=%u\n", mac3, ir3 &0xffff, flag, f22);cester_assert_int_eq(32768, mac3);cester_assert_uint_eq(0x7fff, ir3);cester_assert_uint_eq(0, f22);uint32_t f17=(flag > > 17) &1;cester_assert_uint_eq(1, f17);) CESTER_TEST(prec_rtps_sf0_ir3_flag_strong | |
| cop2_putc (26, 200) | |
| cop2_put (0, 0x00000000) | |
| cop2_put (1, 16) | |
| cop2_cmd (COP2_RTPS(0, 0)) | |
| cop2_get (27, mac3) | |
| cop2_get (11, ir3) | |
| cester_assert_uint_eq (0x7fff, ir3) | |
| cester_assert_uint_eq (0, f22) | |
Variables | |
| gte_tests | |
| uint32_t | flag = gte_read_flag() |
| uint32_t | f27 = (flag >> 27) & 1 |
| uint32_t | f28 = (flag >> 28) & 1 |
| uint32_t | sxy2 |
| int16_t | sx = (int16_t)(sxy2 & 0xffff) |
| uint32_t | f17 = (flag >> 17) & 1 |
| int32_t | ir1 |
| int32_t | mac3 |
| uint32_t | ir3 |
| uint32_t | f22 = (flag >> 22) & 1 |
| cester_assert_int_eq | ( | 1 | , |
| sx | |||
| ) |
| cester_assert_uint_eq | ( | 0 | , |
| f17 | |||
| ) |
| cester_assert_uint_eq | ( | 0 | , |
| f22 | |||
| ) |
| cester_assert_uint_eq | ( | 0x7fff | , |
| ir3 | |||
| ) |
| cester_assert_uint_eq | ( | 1 | , |
| f27 | |||
| ) |
| cester_assert_uint_eq | ( | 1 | , |
| f28 | |||
| ) |
| CESTER_TEST | ( | prec_div_100_over_1000 | , |
| gte_tests | , | ||
| gte_set_identity_rotation();gte_set_translation(0, 0, 0);cop2_putc(24, 0);cop2_putc(25, 0);cop2_putc(26, 100);cop2_putc(27, 0);cop2_putc(28, 0);cop2_put(0,(0<< 16)|1000);cop2_put(1, 1000);gte_clear_flag();cop2_cmd(COP2_RTPS(1, 0));uint32_t sxy2;cop2_get(14, sxy2);int16_t | sx = (int16_t)(sxy2 & 0xffff); ramsyscall_printf("div 100/1000: SX=%d\n", sx); cester_assert_int_eq(100, sx); |
||
| ) |
| CESTER_TEST | ( | prec_div_large_h | , |
| gte_tests | , | ||
| gte_set_identity_rotation();gte_set_translation(0, 0, 0);cop2_putc(24, 0);cop2_putc(25, 0);cop2_putc(26, 0xfffe);cop2_putc(27, 0);cop2_putc(28, 0);cop2_put(0,(0<< 16)|1);cop2_put(1, 0x7fff);gte_clear_flag();cop2_cmd(COP2_RTPS(1, 0));uint32_t flag; | flag = gte_read_flag(); uint32_t f17 = (flag >> 17) & 1; ramsyscall_printf("div large H: FLAG=0x%08x F17=%u\n", flag, f17); cester_assert_uint_eq(1, f17); |
||
| ) |
| CESTER_TEST | ( | prec_mac1_positive_overflow | , |
| gte_tests | , | ||
| cop2_putc(0, 0x00007fff);cop2_putc(1, 0x00000000);cop2_putc(2, 0x00000000);cop2_putc(3, 0x00000000);cop2_putc(4, 0);cop2_putc(5, 0x7fffffff);cop2_putc(6, 0);cop2_putc(7, 0);cop2_put(0,(0<< 16)|0x7fff);cop2_put(1, 0);gte_clear_flag();cop2_cmd(COP2_MVMVA(0, COP2_MX_RT, COP2_V_V0, COP2_CV_TR, 0));uint32_t | flag = gte_read_flag(); uint32_t f30 = (flag >> 30) & 1; ramsyscall_printf("MAC1 pos overflow: FLAG=0x%08x F30=%u\n", flag, f30); cester_assert_uint_eq(1, f30); |
||
| ) |
| CESTER_TEST | ( | prec_mac2_overflow | , |
| gte_tests | , | ||
| cop2_putc(0, 0x00000000);cop2_putc(1, 0x7fff0000);cop2_putc(2, 0x00000000);cop2_putc(3, 0x00000000);cop2_putc(4, 0);cop2_putc(5, 0);cop2_putc(6, 0x7fffffff);cop2_putc(7, 0);cop2_put(0,(0<< 16)|0x7fff);cop2_put(1, 0);gte_clear_flag();cop2_cmd(COP2_MVMVA(0, COP2_MX_RT, COP2_V_V0, COP2_CV_TR, 0));uint32_t | flag = gte_read_flag(); uint32_t f29 = (flag >> 29) & 1; ramsyscall_printf("MAC2 pos overflow: FLAG=0x%08x F29=%u\n", flag, f29); cester_assert_uint_eq(1, f29); |
||
| ) |
| CESTER_TEST | ( | prec_mac_double_overflow | , |
| gte_tests | , | ||
| cop2_putc(0, 0x00000000);cop2_putc(2, 0x00007fff);cop2_putc(4, 0x7fff);cop2_put(9, 0);cop2_put(10, 0x7fff);cop2_put(11, 0x7fff);gte_clear_flag();cop2_cmd(COP2_OP_CP(0, 0));int32_t mac1;uint32_t flag;cop2_get(25, mac1); | flag = gte_read_flag(); ramsyscall_printf("double overflow: MAC1=%d FLAG=0x%08x\n", mac1, flag); cester_assert_int_eq(0, mac1); cester_assert_uint_eq(0, flag); |
||
| ) |
| CESTER_TEST | ( | prec_rtps_sf0_ir3_flag_anomaly | , |
| gte_tests | , | ||
| gte_set_identity_rotation();cop2_putc(5, 0);cop2_putc(6, 0);cop2_putc(7, 0);cop2_putc(24, 0);cop2_putc(25, 0);cop2_putc(26, 200);cop2_putc(27, 0);cop2_putc(28, 0);cop2_put(0, 0x00000000);cop2_put(1, 8);gte_clear_flag();cop2_cmd(COP2_RTPS(0, 0));int32_t mac3;uint32_t | ir3, | ||
| flag;cop2_get(27, mac3);cop2_get(11, ir3); | flag = gte_read_flag(); uint32_t f22 = (flag >> 22) & 1; ramsyscall_printf("sf=0 anomaly: MAC3=%d IR3=0x%04x FLAG=0x%08x F22=%u\n", mac3, ir3 & 0xffff, flag, f22); cester_assert_int_eq(32768, mac3); cester_assert_uint_eq(0x7fff, ir3); cester_assert_uint_eq(0, f22); uint32_t f17 = (flag >> 17) & 1; cester_assert_uint_eq(1, f17); |
||
| ) |
| cop2_cmd | ( | COP2_MVMVA(0, COP2_MX_RT, COP2_V_V0, COP2_CV_TR, 0) | ) |
| cop2_cmd | ( | COP2_RTPS(0, 0) | ) |
| cop2_cmd | ( | COP2_RTPS(1, 0) | ) |
| cop2_get | ( | 11 | , |
| ir3 | |||
| ) |
| cop2_get | ( | 14 | , |
| sxy2 | |||
| ) |
| cop2_get | ( | 27 | , |
| mac3 | |||
| ) |
| cop2_get | ( | 9 | , |
| ir1 | |||
| ) |
| cop2_put | ( | 0 | , |
| 0x00000000 | |||
| ) |
| cop2_put | ( | 0 | , |
| (0<< 16)| | 0x8000 | ||
| ) |
| cop2_put | ( | 1 | , |
| 0 | |||
| ) |
| cop2_put | ( | 1 | , |
| 0x780b | |||
| ) |
| cop2_put | ( | 1 | , |
| 1 | |||
| ) |
| cop2_put | ( | 1 | , |
| 16 | |||
| ) |
| cop2_putc | ( | 0 | , |
| 0x00000000 | |||
| ) |
| cop2_putc | ( | 0 | , |
| 0x00007fff | |||
| ) |
| cop2_putc | ( | 1 | , |
| 0x00000000 | |||
| ) |
| cop2_putc | ( | 2 | , |
| 0x00000000 | |||
| ) |
| cop2_putc | ( | 24 | , |
| 0 | |||
| ) |
| cop2_putc | ( | 25 | , |
| 0 | |||
| ) |
| cop2_putc | ( | 26 | , |
| 0xf015 | |||
| ) |
| cop2_putc | ( | 26 | , |
| 1 | |||
| ) |
| cop2_putc | ( | 26 | , |
| 200 | |||
| ) |
| cop2_putc | ( | 27 | , |
| 0 | |||
| ) |
| cop2_putc | ( | 28 | , |
| 0 | |||
| ) |
| cop2_putc | ( | 3 | , |
| 0x00000000 | |||
| ) |
| cop2_putc | ( | 3 | , |
| 0x00007fff | |||
| ) |
| cop2_putc | ( | 4 | , |
| 0 | |||
| ) |
| cop2_putc | ( | 5 | , |
| 0 | |||
| ) |
| cop2_putc | ( | 5 | , |
| 0x80000000 | |||
| ) |
| cop2_putc | ( | 6 | , |
| 0 | |||
| ) |
| cop2_putc | ( | 7 | , |
| 0 | |||
| ) |
| cop2_putc | ( | 7 | , |
| 0x7fffffff | |||
| ) |
| gte_clear_flag | ( | ) |
| gte_set_identity_rotation | ( | ) |
| gte_set_translation | ( | 0 | , |
| 0 | , | ||
| 0 | |||
| ) |
| ramsyscall_printf | ( | ) |
| flag = gte_read_flag() |
| gte_tests |
| int32_t ir1 |
| uint32_t ir3 |
| int32_t mac3 |
| int16_t sx = (int16_t)(sxy2 & 0xffff) |
| uint32_t sxy2 |