cdlreads.c File Reference

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Functions
	CESTER_TEST (cdlReadS1x, test_instances, int resetDone=resetCDRom();if(!resetDone) { cester_assert_true(resetDone);return;} int setLocDone=setLoc(0, 2, 0x16);if(!setLocDone) { cester_assert_true(setLocDone);return;} initializeTime();CDROM_REG0=0;CDROM_REG1=CDL_READS;uint32_t ackTime1=waitCDRomIRQ();uint8_t cause1=ackCDRomCause();uint8_t ctrl1=CDROM_REG0 &~3;uint8_t response1[16];uint8_t responseSize1=readResponse(response1);uint8_t ctrl2=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause1b=CDROM_REG3_UC;uint32_t readyTime=waitCDRomIRQ() - ackTime1;uint8_t cause2=ackCDRomCause();uint8_t ctrl3=CDROM_REG0 &~3;uint8_t response2[16];uint8_t responseSize2=readResponse(response2);uint8_t ctrl4=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause2b=CDROM_REG3_UC;initializeTime();uint8_t sector[2048];uint32_t size=0;CDROM_REG0=0;CDROM_REG3=0x80;while((CDROM_REG0 &0x40)==0);while(((CDROM_REG0 &0x40) !=0) &&(size< 6)) { sector[size++]=CDROM_REG2;} CDROM_REG3=0;uint32_t readTime=updateTime();initializeTime();CDROM_REG0=0;CDROM_REG1=CDL_PAUSE;uint32_t ackTime2=waitCDRomIRQ();uint8_t cause3=ackCDRomCause();uint8_t ctrl5=CDROM_REG0 &~3;uint8_t response3[16];uint8_t responseSize3=readResponse(response3);uint8_t ctrl6=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause3b=CDROM_REG3_UC;uint32_t completeTime=waitCDRomIRQ() - ackTime2;uint8_t cause4=ackCDRomCause();uint8_t ctrl7=CDROM_REG0 &~3;uint8_t response4[16];uint8_t responseSize4=readResponse(response4);uint8_t ctrl8=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause4b=CDROM_REG3_UC;cester_assert_uint_eq(3, cause1);cester_assert_uint_eq(0xe0, cause1b);cester_assert_uint_eq(1, cause2);cester_assert_uint_eq(0xe0, cause2b);cester_assert_uint_eq(3, cause3);cester_assert_uint_eq(0xe0, cause3b);cester_assert_uint_eq(2, cause4);cester_assert_uint_eq(0xe0, cause4b);cester_assert_uint_eq(0x38, ctrl1);cester_assert_uint_eq(0x18, ctrl2);cester_assert_uint_eq(0x38, ctrl3);cester_assert_uint_eq(0x18, ctrl4);cester_assert_uint_eq(0x38, ctrl5);cester_assert_uint_eq(0x18, ctrl6);cester_assert_uint_eq(0x38, ctrl7);cester_assert_uint_eq(0x18, ctrl8);cester_assert_uint_eq(2, response1[0]);cester_assert_uint_eq(1, responseSize1);cester_assert_uint_eq(0x22, response2[0]);cester_assert_uint_eq(1, responseSize2);cester_assert_uint_eq(0x22, response3[0]);cester_assert_uint_eq(1, responseSize3);cester_assert_uint_eq(2, response4[0]);cester_assert_uint_eq(1, responseSize4);cester_assert_uint_ge(ackTime1, 500);cester_assert_uint_lt(ackTime1, 7000);cester_assert_uint_ge(ackTime2, 500);cester_assert_uint_lt(ackTime2, 7000);cester_assert_uint_ge(completeTime, 65000);cester_assert_uint_eq(1, sector[0]);cester_assert_uint_eq('C', sector[1]);cester_assert_uint_eq('D', sector[2]);cester_assert_uint_eq('0', sector[3]);cester_assert_uint_eq('0', sector[4]);cester_assert_uint_eq('1', sector[5]);cester_assert_uint_eq(6, size);ramsyscall_printf("Basic single 6 bytes readS @1x at 00:02:16, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime);) CESTER_TEST(cdlReadS1xwithDMA
	if (!resetDone)
	initializeTime ()
	while ((DMA_CTRL[DMA_CDROM].CHCR &0x01000000) !=0)
	cester_assert_uint_eq (3, cause1)
	cester_assert_uint_eq (0xe0, cause1b)
	cester_assert_uint_eq (1, cause2)
	cester_assert_uint_eq (0xe0, cause2b)
	cester_assert_uint_eq (3, cause3)
	cester_assert_uint_eq (0xe0, cause3b)
	cester_assert_uint_eq (2, cause4)
	cester_assert_uint_eq (0xe0, cause4b)
	cester_assert_uint_eq (0x38, ctrl1)
	cester_assert_uint_eq (0x18, ctrl2)
	cester_assert_uint_eq (0x38, ctrl3)
	cester_assert_uint_eq (0x18, ctrl4)
	cester_assert_uint_eq (0x38, ctrl5)
	cester_assert_uint_eq (0x18, ctrl6)
	cester_assert_uint_eq (0x38, ctrl7)
	cester_assert_uint_eq (0x18, ctrl8)
	cester_assert_uint_eq (2, response1[0])
	cester_assert_uint_eq (1, responseSize1)
	cester_assert_uint_eq (0x22, response2[0])
	cester_assert_uint_eq (1, responseSize2)
	cester_assert_uint_eq (0x22, response3[0])
	cester_assert_uint_eq (1, responseSize3)
	cester_assert_uint_eq (2, response4[0])
	cester_assert_uint_eq (1, responseSize4)
	cester_assert_uint_ge (ackTime1, 500)
	cester_assert_uint_lt (ackTime1, 7000)
	cester_assert_uint_ge (ackTime2, 500)
	cester_assert_uint_lt (ackTime2, 7000)
	cester_assert_uint_ge (completeTime, 65000)
	cester_assert_uint_eq (1, sector[0])
	cester_assert_uint_eq ('C', sector[1])
	cester_assert_uint_eq ('D', sector[2])
	cester_assert_uint_eq ('0', sector[3])
	cester_assert_uint_eq ('0', sector[4])
	cester_assert_uint_eq ('1', sector[5])
	ramsyscall_printf ("Basic single full sector readS @1x with DMA at 00:02:16, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime)
	CESTER_TEST (cdlReadS2x, test_instances, int resetDone=resetCDRom();if(!resetDone) { cester_assert_true(resetDone);return;} int setModeDone=setMode(0x80);if(!setModeDone) { cester_assert_true(setModeDone);return;} int setLocDone=setLoc(0, 2, 0x16);if(!setLocDone) { cester_assert_true(setLocDone);return;} initializeTime();CDROM_REG0=0;CDROM_REG1=CDL_READS;uint32_t ackTime1=waitCDRomIRQ();uint8_t cause1=ackCDRomCause();uint8_t ctrl1=CDROM_REG0 &~3;uint8_t response1[16];uint8_t responseSize1=readResponse(response1);uint8_t ctrl2=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause1b=CDROM_REG3_UC;uint32_t readyTime=waitCDRomIRQ() - ackTime1;uint8_t cause2=ackCDRomCause();uint8_t ctrl3=CDROM_REG0 &~3;uint8_t response2[16];uint8_t responseSize2=readResponse(response2);uint8_t ctrl4=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause2b=CDROM_REG3_UC;initializeTime();uint8_t sector[2048];uint32_t size=0;CDROM_REG0=0;CDROM_REG3=0x80;while((CDROM_REG0 &0x40)==0);while(((CDROM_REG0 &0x40) !=0) &&(size< 6)) { sector[size++]=CDROM_REG2;} CDROM_REG3=0;uint32_t readTime=updateTime();initializeTime();CDROM_REG0=0;CDROM_REG1=CDL_PAUSE;uint32_t ackTime2=waitCDRomIRQ();uint8_t cause3=ackCDRomCause();uint8_t ctrl5=CDROM_REG0 &~3;uint8_t response3[16];uint8_t responseSize3=readResponse(response3);uint8_t ctrl6=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause3b=CDROM_REG3_UC;uint32_t completeTime=waitCDRomIRQ() - ackTime2;uint8_t cause4=ackCDRomCause();uint8_t ctrl7=CDROM_REG0 &~3;uint8_t response4[16];uint8_t responseSize4=readResponse(response4);uint8_t ctrl8=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause4b=CDROM_REG3_UC;cester_assert_uint_eq(3, cause1);cester_assert_uint_eq(0xe0, cause1b);cester_assert_uint_eq(1, cause2);cester_assert_uint_eq(0xe0, cause2b);cester_assert_uint_eq(3, cause3);cester_assert_uint_eq(0xe0, cause3b);cester_assert_uint_eq(2, cause4);cester_assert_uint_eq(0xe0, cause4b);cester_assert_uint_eq(0x38, ctrl1);cester_assert_uint_eq(0x18, ctrl2);cester_assert_uint_eq(0x38, ctrl3);cester_assert_uint_eq(0x18, ctrl4);cester_assert_uint_eq(0x38, ctrl5);cester_assert_uint_eq(0x18, ctrl6);cester_assert_uint_eq(0x38, ctrl7);cester_assert_uint_eq(0x18, ctrl8);cester_assert_uint_eq(2, response1[0]);cester_assert_uint_eq(1, responseSize1);cester_assert_uint_eq(0x22, response2[0]);cester_assert_uint_eq(1, responseSize2);cester_assert_uint_eq(0x22, response3[0]);cester_assert_uint_eq(1, responseSize3);cester_assert_uint_eq(2, response4[0]);cester_assert_uint_eq(1, responseSize4);cester_assert_uint_ge(ackTime1, 500);cester_assert_uint_lt(ackTime1, 7000);cester_assert_uint_ge(ackTime2, 500);cester_assert_uint_lt(ackTime2, 7000);cester_assert_uint_ge(readyTime, 500000);cester_assert_uint_ge(completeTime, 32500);cester_assert_uint_eq(1, sector[0]);cester_assert_uint_eq('C', sector[1]);cester_assert_uint_eq('D', sector[2]);cester_assert_uint_eq('0', sector[3]);cester_assert_uint_eq('0', sector[4]);cester_assert_uint_eq('1', sector[5]);cester_assert_uint_eq(6, size);ramsyscall_printf("Basic single 6 bytes readS @2x at 00:02:16, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime);) CESTER_TEST(cdlReadS2xwithDMA
	cester_assert_uint_ge (readyTime, 500000)
	cester_assert_uint_ge (completeTime, 32500)
	ramsyscall_printf ("Basic single full sector readS @2x with DMA at 00:02:16, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime)
	CESTER_TEST (cdlReadS2xRunaway, test_instances, int resetDone=resetCDRom();if(!resetDone) { cester_assert_true(resetDone);return;} int setModeDone=setMode(0x80);if(!setModeDone) { cester_assert_true(setModeDone);return;} int setLocDone=setLoc(0, 2, 0x16);if(!setLocDone) { cester_assert_true(setLocDone);return;} initializeTime();CDROM_REG0=0;CDROM_REG1=CDL_READS;uint32_t ackTime1=waitCDRomIRQ();uint8_t cause1=ackCDRomCause();uint8_t ctrl1=CDROM_REG0 &~3;uint8_t response1[16];uint8_t responseSize1=readResponse(response1);uint8_t ctrl2=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause1b=CDROM_REG3_UC;uint32_t readyTime=waitCDRomIRQ() - ackTime1;uint8_t cause2=ackCDRomCause();uint8_t ctrl3=CDROM_REG0 &~3;uint8_t response2[16];uint8_t responseSize2=readResponse(response2);uint8_t ctrl4=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause2b=CDROM_REG3_UC;initializeTime();uint8_t sector[2048];uint32_t size=0;CDROM_REG0=0;CDROM_REG3=0x80;while((CDROM_REG0 &0x40)==0);while(((CDROM_REG0 &0x40) !=0) &&(size< 6)) { sector[size++]=CDROM_REG2;} uint32_t readTime=updateTime();initializeTime();CDROM_REG0=0;CDROM_REG1=CDL_PAUSE;uint32_t ackTime2=waitCDRomIRQ();uint8_t cause3=ackCDRomCause();uint8_t ctrl5=CDROM_REG0 &~3;uint8_t response3[16];uint8_t responseSize3=readResponse(response3);uint8_t ctrl6=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause3b=CDROM_REG3_UC;uint32_t completeTime=waitCDRomIRQ() - ackTime2;uint8_t cause4=ackCDRomCause();uint8_t ctrl7=CDROM_REG0 &~3;uint8_t response4[16];uint8_t responseSize4=readResponse(response4);uint8_t ctrl8=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause4b=CDROM_REG3_UC;CDROM_REG0=0;CDROM_REG3=0;cester_assert_uint_eq(3, cause1);cester_assert_uint_eq(0xe0, cause1b);cester_assert_uint_eq(1, cause2);cester_assert_uint_eq(0xe0, cause2b);cester_assert_uint_eq(3, cause3);cester_assert_uint_eq(0xe0, cause3b);cester_assert_uint_eq(2, cause4);cester_assert_uint_eq(0xe0, cause4b);cester_assert_uint_eq(0x38, ctrl1);cester_assert_uint_eq(0x18, ctrl2);cester_assert_uint_eq(0x38, ctrl3);cester_assert_uint_eq(0x18, ctrl4);cester_assert_uint_eq(0x78, ctrl5);cester_assert_uint_eq(0x58, ctrl6);cester_assert_uint_eq(0x78, ctrl7);cester_assert_uint_eq(0x58, ctrl8);cester_assert_uint_eq(2, response1[0]);cester_assert_uint_eq(1, responseSize1);cester_assert_uint_eq(0x22, response2[0]);cester_assert_uint_eq(1, responseSize2);cester_assert_uint_eq(0x22, response3[0]);cester_assert_uint_eq(1, responseSize3);cester_assert_uint_eq(2, response4[0]);cester_assert_uint_eq(1, responseSize4);cester_assert_uint_ge(ackTime1, 500);cester_assert_uint_lt(ackTime1, 7000);cester_assert_uint_ge(ackTime2, 500);cester_assert_uint_lt(ackTime2, 7000);cester_assert_uint_ge(readyTime, 500000);cester_assert_uint_ge(completeTime, 32500);cester_assert_uint_eq(1, sector[0]);cester_assert_uint_eq('C', sector[1]);cester_assert_uint_eq('D', sector[2]);cester_assert_uint_eq('0', sector[3]);cester_assert_uint_eq('0', sector[4]);cester_assert_uint_eq('1', sector[5]);cester_assert_uint_eq(6, size);ramsyscall_printf("Basic single 6 bytes readS @2x at 00:02:16, runaway read, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime);) CESTER_TEST(cdlReadSInAudio
	cester_assert_uint_eq (5, cause2)
	cester_assert_uint_eq (6, response2[0])
	cester_assert_uint_eq (4, response2[1])
	cester_assert_uint_eq (2, responseSize2)
	cester_assert_uint_ge (ackTime, 500)
	cester_assert_uint_lt (ackTime, 7000)
	cester_assert_uint_ge (errorTime, 4000000)
	ramsyscall_printf ("Basic readS in audio track, ack in %ius, errored in %ius\n", ackTime, errorTime)
	CESTER_TEST (cdlReadSTooFar, test_instances, int resetDone=resetCDRom();if(!resetDone) { cester_assert_true(resetDone);return;} int setLocDone=setLoc(0x80, 0, 0);if(!setLocDone) { cester_assert_true(setLocDone);return;} initializeTime();CDROM_REG0=0;CDROM_REG1=CDL_READS;uint32_t ackTime=waitCDRomIRQ();uint8_t cause1=ackCDRomCause();uint8_t ctrl1=CDROM_REG0 &~3;uint8_t response1[16];uint8_t responseSize1=readResponse(response1);uint8_t ctrl2=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause1b=CDROM_REG3_UC;uint32_t errorTime=waitCDRomIRQ() - ackTime;uint8_t cause2=ackCDRomCause();uint8_t ctrl3=CDROM_REG0 &~3;uint8_t response2[16];uint8_t responseSize2=readResponse(response2);uint8_t ctrl4=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause2b=CDROM_REG3_UC;cester_assert_uint_eq(3, cause1);cester_assert_uint_eq(0xe0, cause1b);cester_assert_uint_eq(5, cause2);cester_assert_uint_eq(0xe0, cause2b);cester_assert_uint_eq(0x38, ctrl1);cester_assert_uint_eq(0x18, ctrl2);cester_assert_uint_eq(0x38, ctrl3);cester_assert_uint_eq(0x18, ctrl4);cester_assert_uint_eq(2, response1[0]);cester_assert_uint_eq(1, responseSize1);cester_assert_uint_eq(6, response2[0]);cester_assert_uint_eq(0x10, response2[1]);cester_assert_uint_eq(2, responseSize2);cester_assert_uint_ge(ackTime, 500);cester_assert_uint_lt(ackTime, 7000);cester_assert_uint_ge(errorTime, 600000);ramsyscall_printf("Basic readS too far, ack in %ius, errored in %ius\n", ackTime, errorTime);) CESTER_TEST(cdlReadS2xWithNop
	cester_assert_uint_eq (3, cause2)
	cester_assert_uint_eq (1, cause3)
	cester_assert_uint_eq (3, cause4)
	cester_assert_uint_eq (2, cause5)
	cester_assert_uint_eq (0xe0, cause5b)
	cester_assert_uint_eq (0x98, ctrl2b)
	cester_assert_uint_eq (0x38, ctrl9)
	cester_assert_uint_eq (0x18, ctrl10)
	cester_assert_uint_eq (2, response2[0])
	cester_assert_uint_eq (0x22, response4[0])
	cester_assert_uint_eq (2, response5[0])
	cester_assert_uint_eq (1, responseSize5)
	cester_assert_uint_ge (ackTime3, 500)
	cester_assert_uint_lt (ackTime3, 7000)
	ramsyscall_printf ("Basic single full sector readS @2x with DMA at 70:00:00 with nop interleaved, ack1 in %ius, ack2 in %ius, ready in %ius, ack3 in %ius, complete in %ius\n", ackTime1, ackTime2, readyTime, ackTime3, completeTime)

Variables
	test_instances
int	resetDone = resetCDRom()
int	setLocDone = setLoc(0, 2, 0x16)
	CDROM_REG0 = 0
	CDROM_REG1 = CDL_READS
uint32_t	ackTime1 = waitCDRomIRQ()
uint8_t	cause1 = ackCDRomCause()
uint8_t	ctrl1 = CDROM_REG0 & ~3
uint8_t	response1 [16]
uint8_t	responseSize1 = readResponse(response1)
uint8_t	ctrl2 = CDROM_REG0 & ~3
uint8_t	cause1b = CDROM_REG3_UC
uint32_t	readyTime = waitCDRomIRQ() - ackTime1
uint8_t	cause2 = ackCDRomCause()
uint8_t	ctrl3 = CDROM_REG0 & ~3
uint8_t	response2 [16]
uint8_t	responseSize2 = readResponse(response2)
uint8_t	ctrl4 = CDROM_REG0 & ~3
uint8_t	cause2b = CDROM_REG3_UC
uint8_t	sector [2048]
	CDROM_REG3 = 0x80
uint32_t	dicr = DICR
	DICR = dicr
	DPCR = 0x8000
DMA_CTRL[DMA_CDROM]	MADR = (uintptr_t)sector
DMA_CTRL[DMA_CDROM]	BCR = (2048 >> 2) | 0x10000
DMA_CTRL[DMA_CDROM]	CHCR = 0x11000000
uint32_t	readTime = updateTime()
uint32_t	ackTime2 = waitCDRomIRQ()
uint8_t	cause3 = ackCDRomCause()
uint8_t	ctrl5 = CDROM_REG0 & ~3
uint8_t	response3 [16]
uint8_t	responseSize3 = readResponse(response3)
uint8_t	ctrl6 = CDROM_REG0 & ~3
uint8_t	cause3b = CDROM_REG3_UC
uint32_t	completeTime = waitCDRomIRQ() - ackTime2
uint8_t	cause4 = ackCDRomCause()
uint8_t	ctrl7 = CDROM_REG0 & ~3
uint8_t	response4 [16]
uint8_t	responseSize4 = readResponse(response4)
uint8_t	ctrl8 = CDROM_REG0 & ~3
uint8_t	cause4b = CDROM_REG3_UC
int	setModeDone = setMode(0x80)
uint32_t	ackTime = waitCDRomIRQ()
uint32_t	errorTime = waitCDRomIRQ() - ackTime
uint8_t	ctrl2b = CDROM_REG0 & ~3
uint32_t	ackTime3 = waitCDRomIRQ()
uint8_t	cause5 = ackCDRomCause()
uint8_t	ctrl9 = CDROM_REG0 & ~3
uint8_t	response5 [16]
uint8_t	responseSize5 = readResponse(response5)
uint8_t	ctrl10 = CDROM_REG0 & ~3
uint8_t	cause5b = CDROM_REG3_UC

Function Documentation

cester_assert_uint_eq() [1/46]

cester_assert_uint_eq	(	'0'	,
		sector	[3]
	)

cester_assert_uint_eq() [2/46]

cester_assert_uint_eq	(	'0'	,
		sector	[4]
	)

cester_assert_uint_eq() [3/46]

cester_assert_uint_eq	(	'1'	,
		sector	[5]
	)

cester_assert_uint_eq() [4/46]

cester_assert_uint_eq	(	'C'	,
		sector	[1]
	)

cester_assert_uint_eq() [5/46]

cester_assert_uint_eq	(	'D'	,
		sector	[2]
	)

cester_assert_uint_eq() [6/46]

cester_assert_uint_eq	(	0x18	,
		ctrl10
	)

cester_assert_uint_eq() [7/46]

cester_assert_uint_eq	(	0x18	,
		ctrl2
	)

cester_assert_uint_eq() [8/46]

cester_assert_uint_eq	(	0x18	,
		ctrl4
	)

cester_assert_uint_eq() [9/46]

cester_assert_uint_eq	(	0x18	,
		ctrl6
	)

cester_assert_uint_eq() [10/46]

cester_assert_uint_eq	(	0x18	,
		ctrl8
	)

cester_assert_uint_eq() [11/46]

cester_assert_uint_eq	(	0x22	,
		response2	[0]
	)

cester_assert_uint_eq() [12/46]

cester_assert_uint_eq	(	0x22	,
		response3	[0]
	)

cester_assert_uint_eq() [13/46]

cester_assert_uint_eq	(	0x22	,
		response4	[0]
	)

cester_assert_uint_eq() [14/46]

cester_assert_uint_eq	(	0x38	,
		ctrl1
	)

cester_assert_uint_eq() [15/46]

cester_assert_uint_eq	(	0x38	,
		ctrl3
	)

cester_assert_uint_eq() [16/46]

cester_assert_uint_eq	(	0x38	,
		ctrl5
	)

cester_assert_uint_eq() [17/46]

cester_assert_uint_eq	(	0x38	,
		ctrl7
	)

cester_assert_uint_eq() [18/46]

cester_assert_uint_eq	(	0x38	,
		ctrl9
	)

cester_assert_uint_eq() [19/46]

cester_assert_uint_eq	(	0x98	,
		ctrl2b
	)

cester_assert_uint_eq() [20/46]

cester_assert_uint_eq	(	0xe0	,
		cause1b
	)

cester_assert_uint_eq() [21/46]

cester_assert_uint_eq	(	0xe0	,
		cause2b
	)

cester_assert_uint_eq() [22/46]

cester_assert_uint_eq	(	0xe0	,
		cause3b
	)

cester_assert_uint_eq() [23/46]

cester_assert_uint_eq	(	0xe0	,
		cause4b
	)

cester_assert_uint_eq() [24/46]

cester_assert_uint_eq	(	0xe0	,
		cause5b
	)

cester_assert_uint_eq() [25/46]

cester_assert_uint_eq	(	1	,
		cause2
	)

cester_assert_uint_eq() [26/46]

cester_assert_uint_eq	(	1	,
		cause3
	)

cester_assert_uint_eq() [27/46]

cester_assert_uint_eq	(	1	,
		responseSize1
	)

cester_assert_uint_eq() [28/46]

cester_assert_uint_eq	(	1	,
		responseSize2
	)

cester_assert_uint_eq() [29/46]

cester_assert_uint_eq	(	1	,
		responseSize3
	)

cester_assert_uint_eq() [30/46]

cester_assert_uint_eq	(	1	,
		responseSize4
	)

cester_assert_uint_eq() [31/46]

cester_assert_uint_eq	(	1	,
		responseSize5
	)

cester_assert_uint_eq() [32/46]

cester_assert_uint_eq	(	1	,
		sector	[0]
	)

cester_assert_uint_eq() [33/46]

cester_assert_uint_eq	(	2	,
		cause4
	)

cester_assert_uint_eq() [34/46]

cester_assert_uint_eq	(	2	,
		cause5
	)

cester_assert_uint_eq() [35/46]

cester_assert_uint_eq	(	2	,
		response1	[0]
	)

cester_assert_uint_eq() [36/46]

cester_assert_uint_eq	(	2	,
		response2	[0]
	)

cester_assert_uint_eq() [37/46]

cester_assert_uint_eq	(	2	,
		response4	[0]
	)

cester_assert_uint_eq() [38/46]

cester_assert_uint_eq	(	2	,
		response5	[0]
	)

cester_assert_uint_eq() [39/46]

cester_assert_uint_eq	(	2	,
		responseSize2
	)

cester_assert_uint_eq() [40/46]

cester_assert_uint_eq	(	3	,
		cause1
	)

cester_assert_uint_eq() [41/46]

cester_assert_uint_eq	(	3	,
		cause2
	)

cester_assert_uint_eq() [42/46]

cester_assert_uint_eq	(	3	,
		cause3
	)

cester_assert_uint_eq() [43/46]

cester_assert_uint_eq	(	3	,
		cause4
	)

cester_assert_uint_eq() [44/46]

cester_assert_uint_eq	(	4	,
		response2	[1]
	)

cester_assert_uint_eq() [45/46]

cester_assert_uint_eq	(	5	,
		cause2
	)

cester_assert_uint_eq() [46/46]

cester_assert_uint_eq	(	6	,
		response2	[0]
	)

cester_assert_uint_ge() [1/8]

cester_assert_uint_ge	(	ackTime	,
		500
	)

cester_assert_uint_ge() [2/8]

cester_assert_uint_ge	(	ackTime1	,
		500
	)

cester_assert_uint_ge() [3/8]

cester_assert_uint_ge	(	ackTime2	,
		500
	)

cester_assert_uint_ge() [4/8]

cester_assert_uint_ge	(	ackTime3	,
		500
	)

cester_assert_uint_ge() [5/8]

cester_assert_uint_ge	(	completeTime	,
		32500
	)

cester_assert_uint_ge() [6/8]

cester_assert_uint_ge	(	completeTime	,
		65000
	)

cester_assert_uint_ge() [7/8]

cester_assert_uint_ge	(	errorTime	,
		4000000
	)

cester_assert_uint_ge() [8/8]

cester_assert_uint_ge	(	readyTime	,
		500000
	)

cester_assert_uint_lt() [1/4]

cester_assert_uint_lt	(	ackTime	,
		7000
	)

cester_assert_uint_lt() [2/4]

cester_assert_uint_lt	(	ackTime1	,
		7000
	)

cester_assert_uint_lt() [3/4]

cester_assert_uint_lt	(	ackTime2	,
		7000
	)

cester_assert_uint_lt() [4/4]

cester_assert_uint_lt	(	ackTime3	,
		7000
	)

CESTER_TEST() [1/4]

CESTER_TEST	(	cdlReadS1x	,
		test_instances	,
		int	resetDone = resetCDRom(); if (!resetDone) { cester_assert_true(resetDone); return; } int setLocDone = setLoc(0, 2, 0x16); if (!setLocDone) { cester_assert_true(setLocDone); return; } initializeTime(); CDROM_REG0 = 0; CDROM_REG1 = CDL_READS; uint32_t ackTime1 = waitCDRomIRQ(); uint8_t cause1 = ackCDRomCause(); uint8_t ctrl1 = CDROM_REG0 & ~3; uint8_t response1[16]; uint8_t responseSize1 = readResponse(response1); uint8_t ctrl2 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause1b = CDROM_REG3_UC; uint32_t readyTime = waitCDRomIRQ() - ackTime1; uint8_t cause2 = ackCDRomCause(); uint8_t ctrl3 = CDROM_REG0 & ~3; uint8_t response2[16]; uint8_t responseSize2 = readResponse(response2); uint8_t ctrl4 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause2b = CDROM_REG3_UC; initializeTime(); uint8_t sector[2048]; uint32_t size = 0; CDROM_REG0 = 0; CDROM_REG3 = 0x80; while ((CDROM_REG0 & 0x40) == 0); while (((CDROM_REG0 & 0x40) != 0) && (size < 6)) { sector[size++] = CDROM_REG2; } CDROM_REG3 = 0; uint32_t readTime = updateTime(); initializeTime(); CDROM_REG0 = 0; CDROM_REG1 = CDL_PAUSE; uint32_t ackTime2 = waitCDRomIRQ(); uint8_t cause3 = ackCDRomCause(); uint8_t ctrl5 = CDROM_REG0 & ~3; uint8_t response3[16]; uint8_t responseSize3 = readResponse(response3); uint8_t ctrl6 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause3b = CDROM_REG3_UC; uint32_t completeTime = waitCDRomIRQ() - ackTime2; uint8_t cause4 = ackCDRomCause(); uint8_t ctrl7 = CDROM_REG0 & ~3; uint8_t response4[16]; uint8_t responseSize4 = readResponse(response4); uint8_t ctrl8 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause4b = CDROM_REG3_UC; cester_assert_uint_eq(3, cause1); cester_assert_uint_eq(0xe0, cause1b); cester_assert_uint_eq(1, cause2); cester_assert_uint_eq(0xe0, cause2b); cester_assert_uint_eq(3, cause3); cester_assert_uint_eq(0xe0, cause3b); cester_assert_uint_eq(2, cause4); cester_assert_uint_eq(0xe0, cause4b); cester_assert_uint_eq(0x38, ctrl1); cester_assert_uint_eq(0x18, ctrl2); cester_assert_uint_eq(0x38, ctrl3); cester_assert_uint_eq(0x18, ctrl4); cester_assert_uint_eq(0x38, ctrl5); cester_assert_uint_eq(0x18, ctrl6); cester_assert_uint_eq(0x38, ctrl7); cester_assert_uint_eq(0x18, ctrl8); cester_assert_uint_eq(2, response1[0]); cester_assert_uint_eq(1, responseSize1); cester_assert_uint_eq(0x22, response2[0]); cester_assert_uint_eq(1, responseSize2); cester_assert_uint_eq(0x22, response3[0]); cester_assert_uint_eq(1, responseSize3); cester_assert_uint_eq(2, response4[0]); cester_assert_uint_eq(1, responseSize4); cester_assert_uint_ge(ackTime1, 500); cester_assert_uint_lt(ackTime1, 7000); cester_assert_uint_ge(ackTime2, 500); cester_assert_uint_lt(ackTime2, 7000);  cester_assert_uint_ge(completeTime, 65000); cester_assert_uint_eq(1, sector[0]); cester_assert_uint_eq('C', sector[1]); cester_assert_uint_eq('D', sector[2]); cester_assert_uint_eq('0', sector[3]); cester_assert_uint_eq('0', sector[4]); cester_assert_uint_eq('1', sector[5]); cester_assert_uint_eq(6, size); ramsyscall_printf("Basic single 6 bytes readS @1x at 00:02:16, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime);
	)

CESTER_TEST() [2/4]

CESTER_TEST	(	cdlReadS2x	,
		test_instances	,
		int	resetDone = resetCDRom(); if (!resetDone) { cester_assert_true(resetDone); return; } int setModeDone = setMode(0x80); if (!setModeDone) { cester_assert_true(setModeDone); return; } int setLocDone = setLoc(0, 2, 0x16); if (!setLocDone) { cester_assert_true(setLocDone); return; } initializeTime(); CDROM_REG0 = 0; CDROM_REG1 = CDL_READS; uint32_t ackTime1 = waitCDRomIRQ(); uint8_t cause1 = ackCDRomCause(); uint8_t ctrl1 = CDROM_REG0 & ~3; uint8_t response1[16]; uint8_t responseSize1 = readResponse(response1); uint8_t ctrl2 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause1b = CDROM_REG3_UC; uint32_t readyTime = waitCDRomIRQ() - ackTime1; uint8_t cause2 = ackCDRomCause(); uint8_t ctrl3 = CDROM_REG0 & ~3; uint8_t response2[16]; uint8_t responseSize2 = readResponse(response2); uint8_t ctrl4 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause2b = CDROM_REG3_UC; initializeTime(); uint8_t sector[2048]; uint32_t size = 0; CDROM_REG0 = 0; CDROM_REG3 = 0x80; while ((CDROM_REG0 & 0x40) == 0); while (((CDROM_REG0 & 0x40) != 0) && (size < 6)) { sector[size++] = CDROM_REG2; } CDROM_REG3 = 0; uint32_t readTime = updateTime(); initializeTime(); CDROM_REG0 = 0; CDROM_REG1 = CDL_PAUSE; uint32_t ackTime2 = waitCDRomIRQ(); uint8_t cause3 = ackCDRomCause(); uint8_t ctrl5 = CDROM_REG0 & ~3; uint8_t response3[16]; uint8_t responseSize3 = readResponse(response3); uint8_t ctrl6 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause3b = CDROM_REG3_UC; uint32_t completeTime = waitCDRomIRQ() - ackTime2; uint8_t cause4 = ackCDRomCause(); uint8_t ctrl7 = CDROM_REG0 & ~3; uint8_t response4[16]; uint8_t responseSize4 = readResponse(response4); uint8_t ctrl8 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause4b = CDROM_REG3_UC; cester_assert_uint_eq(3, cause1); cester_assert_uint_eq(0xe0, cause1b); cester_assert_uint_eq(1, cause2); cester_assert_uint_eq(0xe0, cause2b); cester_assert_uint_eq(3, cause3); cester_assert_uint_eq(0xe0, cause3b); cester_assert_uint_eq(2, cause4); cester_assert_uint_eq(0xe0, cause4b); cester_assert_uint_eq(0x38, ctrl1); cester_assert_uint_eq(0x18, ctrl2); cester_assert_uint_eq(0x38, ctrl3); cester_assert_uint_eq(0x18, ctrl4); cester_assert_uint_eq(0x38, ctrl5); cester_assert_uint_eq(0x18, ctrl6); cester_assert_uint_eq(0x38, ctrl7); cester_assert_uint_eq(0x18, ctrl8); cester_assert_uint_eq(2, response1[0]); cester_assert_uint_eq(1, responseSize1); cester_assert_uint_eq(0x22, response2[0]); cester_assert_uint_eq(1, responseSize2); cester_assert_uint_eq(0x22, response3[0]); cester_assert_uint_eq(1, responseSize3); cester_assert_uint_eq(2, response4[0]); cester_assert_uint_eq(1, responseSize4); cester_assert_uint_ge(ackTime1, 500); cester_assert_uint_lt(ackTime1, 7000); cester_assert_uint_ge(ackTime2, 500); cester_assert_uint_lt(ackTime2, 7000);    cester_assert_uint_ge(readyTime, 500000);  cester_assert_uint_ge(completeTime, 32500); cester_assert_uint_eq(1, sector[0]); cester_assert_uint_eq('C', sector[1]); cester_assert_uint_eq('D', sector[2]); cester_assert_uint_eq('0', sector[3]); cester_assert_uint_eq('0', sector[4]); cester_assert_uint_eq('1', sector[5]); cester_assert_uint_eq(6, size); ramsyscall_printf("Basic single 6 bytes readS @2x at 00:02:16, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime);
	)

CESTER_TEST() [3/4]

CESTER_TEST	(	cdlReadS2xRunaway	,
		test_instances	,
		int	resetDone = resetCDRom(); if (!resetDone) { cester_assert_true(resetDone); return; } int setModeDone = setMode(0x80); if (!setModeDone) { cester_assert_true(setModeDone); return; } int setLocDone = setLoc(0, 2, 0x16); if (!setLocDone) { cester_assert_true(setLocDone); return; } initializeTime(); CDROM_REG0 = 0; CDROM_REG1 = CDL_READS; uint32_t ackTime1 = waitCDRomIRQ(); uint8_t cause1 = ackCDRomCause(); uint8_t ctrl1 = CDROM_REG0 & ~3; uint8_t response1[16]; uint8_t responseSize1 = readResponse(response1); uint8_t ctrl2 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause1b = CDROM_REG3_UC; uint32_t readyTime = waitCDRomIRQ() - ackTime1; uint8_t cause2 = ackCDRomCause(); uint8_t ctrl3 = CDROM_REG0 & ~3; uint8_t response2[16]; uint8_t responseSize2 = readResponse(response2); uint8_t ctrl4 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause2b = CDROM_REG3_UC; initializeTime(); uint8_t sector[2048]; uint32_t size = 0; CDROM_REG0 = 0; CDROM_REG3 = 0x80; while ((CDROM_REG0 & 0x40) == 0); while (((CDROM_REG0 & 0x40) != 0) && (size < 6)) { sector[size++] = CDROM_REG2; } uint32_t readTime = updateTime(); initializeTime(); CDROM_REG0 = 0; CDROM_REG1 = CDL_PAUSE; uint32_t ackTime2 = waitCDRomIRQ(); uint8_t cause3 = ackCDRomCause(); uint8_t ctrl5 = CDROM_REG0 & ~3; uint8_t response3[16]; uint8_t responseSize3 = readResponse(response3); uint8_t ctrl6 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause3b = CDROM_REG3_UC; uint32_t completeTime = waitCDRomIRQ() - ackTime2; uint8_t cause4 = ackCDRomCause(); uint8_t ctrl7 = CDROM_REG0 & ~3; uint8_t response4[16]; uint8_t responseSize4 = readResponse(response4); uint8_t ctrl8 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause4b = CDROM_REG3_UC; CDROM_REG0 = 0; CDROM_REG3 = 0; cester_assert_uint_eq(3, cause1); cester_assert_uint_eq(0xe0, cause1b); cester_assert_uint_eq(1, cause2); cester_assert_uint_eq(0xe0, cause2b); cester_assert_uint_eq(3, cause3); cester_assert_uint_eq(0xe0, cause3b); cester_assert_uint_eq(2, cause4); cester_assert_uint_eq(0xe0, cause4b); cester_assert_uint_eq(0x38, ctrl1); cester_assert_uint_eq(0x18, ctrl2); cester_assert_uint_eq(0x38, ctrl3); cester_assert_uint_eq(0x18, ctrl4); cester_assert_uint_eq(0x78, ctrl5); cester_assert_uint_eq(0x58, ctrl6); cester_assert_uint_eq(0x78, ctrl7); cester_assert_uint_eq(0x58, ctrl8); cester_assert_uint_eq(2, response1[0]); cester_assert_uint_eq(1, responseSize1); cester_assert_uint_eq(0x22, response2[0]); cester_assert_uint_eq(1, responseSize2); cester_assert_uint_eq(0x22, response3[0]); cester_assert_uint_eq(1, responseSize3); cester_assert_uint_eq(2, response4[0]); cester_assert_uint_eq(1, responseSize4); cester_assert_uint_ge(ackTime1, 500); cester_assert_uint_lt(ackTime1, 7000); cester_assert_uint_ge(ackTime2, 500); cester_assert_uint_lt(ackTime2, 7000);    cester_assert_uint_ge(readyTime, 500000);  cester_assert_uint_ge(completeTime, 32500); cester_assert_uint_eq(1, sector[0]); cester_assert_uint_eq('C', sector[1]); cester_assert_uint_eq('D', sector[2]); cester_assert_uint_eq('0', sector[3]); cester_assert_uint_eq('0', sector[4]); cester_assert_uint_eq('1', sector[5]); cester_assert_uint_eq(6, size); ramsyscall_printf("Basic single 6 bytes readS @2x at 00:02:16, runaway read, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime);
	)

CESTER_TEST() [4/4]

CESTER_TEST	(	cdlReadSTooFar	,
		test_instances	,
		int	resetDone = resetCDRom(); if (!resetDone) { cester_assert_true(resetDone); return; } int setLocDone = setLoc(0x80, 0, 0); if (!setLocDone) { cester_assert_true(setLocDone); return; } initializeTime(); CDROM_REG0 = 0; CDROM_REG1 = CDL_READS; uint32_t ackTime = waitCDRomIRQ(); uint8_t cause1 = ackCDRomCause(); uint8_t ctrl1 = CDROM_REG0 & ~3; uint8_t response1[16]; uint8_t responseSize1 = readResponse(response1); uint8_t ctrl2 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause1b = CDROM_REG3_UC; uint32_t errorTime = waitCDRomIRQ() - ackTime; uint8_t cause2 = ackCDRomCause(); uint8_t ctrl3 = CDROM_REG0 & ~3; uint8_t response2[16]; uint8_t responseSize2 = readResponse(response2); uint8_t ctrl4 = CDROM_REG0 & ~3; CDROM_REG0 = 1; uint8_t cause2b = CDROM_REG3_UC; cester_assert_uint_eq(3, cause1); cester_assert_uint_eq(0xe0, cause1b); cester_assert_uint_eq(5, cause2); cester_assert_uint_eq(0xe0, cause2b); cester_assert_uint_eq(0x38, ctrl1); cester_assert_uint_eq(0x18, ctrl2); cester_assert_uint_eq(0x38, ctrl3); cester_assert_uint_eq(0x18, ctrl4); cester_assert_uint_eq(2, response1[0]); cester_assert_uint_eq(1, responseSize1); cester_assert_uint_eq(6, response2[0]); cester_assert_uint_eq(0x10, response2[1]); cester_assert_uint_eq(2, responseSize2); cester_assert_uint_ge(ackTime, 500); cester_assert_uint_lt(ackTime, 7000); cester_assert_uint_ge(errorTime, 600000); ramsyscall_printf("Basic readS too far, ack in %ius, errored in %ius\n", ackTime, errorTime);
	)

if()

if

(

!

resetDone

)

initializeTime()

initializeTime

(

)

ramsyscall_printf() [1/4]

ramsyscall_printf	(	"Basic readS in audio	track,
		ack in %	ius,
		errored in %ius\n"	,
		ackTime	,
		errorTime
	)

ramsyscall_printf() [2/4]

ramsyscall_printf	(	"Basic single full sector readS @1x with DMA at 00:02:16	,
		ack1 in %	ius,
		ready in %	ius,
		read in %	ius,
		ack2 in %	ius,
		complete in %ius\n"	,
		ackTime1	,
		readyTime	,
		readTime	,
		ackTime2	,
		completeTime
	)

ramsyscall_printf() [3/4]

ramsyscall_printf	(	"Basic single full sector readS @2x with DMA at 00:02:16	,
		ack1 in %	ius,
		ready in %	ius,
		read in %	ius,
		ack2 in %	ius,
		complete in %ius\n"	,
		ackTime1	,
		readyTime	,
		readTime	,
		ackTime2	,
		completeTime
	)

ramsyscall_printf() [4/4]

ramsyscall_printf	(	"Basic single full sector readS @2x with DMA at 70:00:00 with nop	interleaved,
		ack1 in %	ius,
		ack2 in %	ius,
		ready in %	ius,
		ack3 in %	ius,
		complete in %ius\n"	,
		ackTime1	,
		ackTime2	,
		readyTime	,
		ackTime3	,
		completeTime
	)

while()

while

(

(DMA_CTRL[DMA_CDROM].CHCR &0x01000000) !

= 0

)

Variable Documentation

ackTime

uint32_t ackTime = waitCDRomIRQ()

ackTime1

uint32_t ackTime1 = waitCDRomIRQ()

ackTime2

uint32_t ackTime2 = waitCDRomIRQ()

ackTime3

uint32_t ackTime3 = waitCDRomIRQ()

BCR

DMA_CTRL [DMA_CDROM] BCR = (2048 >> 2) | 0x10000

cause1

uint8_t cause1 = ackCDRomCause()

cause1b

uint8_t cause1b = CDROM_REG3_UC

cause2

uint8_t cause2 = ackCDRomCause()

cause2b

uint8_t cause2b = CDROM_REG3_UC

cause3

uint8_t cause3 = ackCDRomCause()

cause3b

uint8_t cause3b = CDROM_REG3_UC

cause4

uint8_t cause4 = ackCDRomCause()

cause4b

uint8_t cause4b = CDROM_REG3_UC

cause5

uint8_t cause5 = ackCDRomCause()

cause5b

uint8_t cause5b = CDROM_REG3_UC

CDROM_REG0

CDROM_REG0 = 0

CDROM_REG1

CDROM_REG1 = CDL_READS

CDROM_REG3

CDROM_REG3 = 0x80

CHCR

DMA_CTRL [DMA_CDROM] CHCR = 0x11000000

completeTime

uint32_t completeTime = waitCDRomIRQ() - ackTime2

ctrl1

uint8_t ctrl1 = CDROM_REG0 & ~3

ctrl10

uint8_t ctrl10 = CDROM_REG0 & ~3

ctrl2

uint8_t ctrl2 = CDROM_REG0 & ~3

ctrl2b

uint8_t ctrl2b = CDROM_REG0 & ~3

ctrl3

uint8_t ctrl3 = CDROM_REG0 & ~3

ctrl4

uint8_t ctrl4 = CDROM_REG0 & ~3

ctrl5

uint8_t ctrl5 = CDROM_REG0 & ~3

ctrl6

uint8_t ctrl6 = CDROM_REG0 & ~3

ctrl7

uint8_t ctrl7 = CDROM_REG0 & ~3

ctrl8

uint8_t ctrl8 = CDROM_REG0 & ~3

ctrl9

uint8_t ctrl9 = CDROM_REG0 & ~3

dicr

dicr& dicr = DICR

DICR

DICR = dicr

DPCR

DPCR = 0x8000

errorTime

uint32_t errorTime = waitCDRomIRQ() - ackTime

MADR

DMA_CTRL [DMA_CDROM] MADR = (uintptr_t)sector

readTime

uint32_t readTime = updateTime()

readyTime

uint32_t readyTime = waitCDRomIRQ() - ackTime1

resetDone

int resetDone = resetCDRom()

response1

uint8_t response1[16]

response2

uint8_t response2[16]

response3

uint8_t response3[16]

response4

uint8_t response4[16]

response5

uint8_t response5[16]

responseSize1

uint8_t responseSize1 = readResponse(response1)

responseSize2

uint8_t responseSize2 = readResponse(response2)

responseSize3

uint8_t responseSize3 = readResponse(response3)

responseSize4

uint8_t responseSize4 = readResponse(response4)

responseSize5

uint8_t responseSize5 = readResponse(response5)

sector

uint8_t sector[2048]

setLocDone

int setLocDone = setLoc(0, 2, 0x16)

setModeDone

int setModeDone = setMode(0x80)

test_instances

test_instances