Nugget
Bare-metal libraries and examples for the original PlayStation
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cdlreads.c
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1/*
2
3MIT License
4
5Copyright (c) 2022 PCSX-Redux authors
6
7Permission is hereby granted, free of charge, to any person obtaining a copy
8of this software and associated documentation files (the "Software"), to deal
9in the Software without restriction, including without limitation the rights
10to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11copies of the Software, and to permit persons to whom the Software is
12furnished to do so, subject to the following conditions:
13
14The above copyright notice and this permission notice shall be included in all
15copies or substantial portions of the Software.
16
17THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23SOFTWARE.
24
25*/
26
27// clang-format off
28
29CESTER_TEST(cdlReadS1x, test_instances,
30 int resetDone = resetCDRom();
31 if (!resetDone) {
32 cester_assert_true(resetDone);
33 return;
34 }
35
36 int setLocDone = setLoc(0, 2, 0x16);
37 if (!setLocDone) {
38 cester_assert_true(setLocDone);
39 return;
40 }
41
42 initializeTime();
43 CDROM_REG0 = 0;
44 CDROM_REG1 = CDL_READS;
45 uint32_t ackTime1 = waitCDRomIRQ();
46 uint8_t cause1 = ackCDRomCause();
47 uint8_t ctrl1 = CDROM_REG0 & ~3;
48 uint8_t response1[16];
49 uint8_t responseSize1 = readResponse(response1);
50 uint8_t ctrl2 = CDROM_REG0 & ~3;
51 CDROM_REG0 = 1;
52 uint8_t cause1b = CDROM_REG3_UC;
53
54 uint32_t readyTime = waitCDRomIRQ() - ackTime1;
55 uint8_t cause2 = ackCDRomCause();
56 uint8_t ctrl3 = CDROM_REG0 & ~3;
57 uint8_t response2[16];
58 uint8_t responseSize2 = readResponse(response2);
59 uint8_t ctrl4 = CDROM_REG0 & ~3;
60 CDROM_REG0 = 1;
61 uint8_t cause2b = CDROM_REG3_UC;
62
63 initializeTime();
64 uint8_t sector[2048];
65 uint32_t size = 0;
66
67 CDROM_REG0 = 0;
68 CDROM_REG3 = 0x80;
69
70 while ((CDROM_REG0 & 0x40) == 0);
71 while (((CDROM_REG0 & 0x40) != 0) && (size < 6)) {
72 sector[size++] = CDROM_REG2;
73 }
74 CDROM_REG3 = 0;
75 uint32_t readTime = updateTime();
76
77 initializeTime();
78 CDROM_REG0 = 0;
79 CDROM_REG1 = CDL_PAUSE;
80 uint32_t ackTime2 = waitCDRomIRQ();
81 uint8_t cause3 = ackCDRomCause();
82 uint8_t ctrl5 = CDROM_REG0 & ~3;
83 uint8_t response3[16];
84 uint8_t responseSize3 = readResponse(response3);
85 uint8_t ctrl6 = CDROM_REG0 & ~3;
86 CDROM_REG0 = 1;
87 uint8_t cause3b = CDROM_REG3_UC;
88
89 uint32_t completeTime = waitCDRomIRQ() - ackTime2;
90 uint8_t cause4 = ackCDRomCause();
91 uint8_t ctrl7 = CDROM_REG0 & ~3;
92 uint8_t response4[16];
93 uint8_t responseSize4 = readResponse(response4);
94 uint8_t ctrl8 = CDROM_REG0 & ~3;
95 CDROM_REG0 = 1;
96 uint8_t cause4b = CDROM_REG3_UC;
97
98 cester_assert_uint_eq(3, cause1);
99 cester_assert_uint_eq(0xe0, cause1b);
100 cester_assert_uint_eq(1, cause2);
101 cester_assert_uint_eq(0xe0, cause2b);
102 cester_assert_uint_eq(3, cause3);
103 cester_assert_uint_eq(0xe0, cause3b);
104 cester_assert_uint_eq(2, cause4);
105 cester_assert_uint_eq(0xe0, cause4b);
106 cester_assert_uint_eq(0x38, ctrl1);
107 cester_assert_uint_eq(0x18, ctrl2);
108 cester_assert_uint_eq(0x38, ctrl3);
109 cester_assert_uint_eq(0x18, ctrl4);
110 cester_assert_uint_eq(0x38, ctrl5);
111 cester_assert_uint_eq(0x18, ctrl6);
112 cester_assert_uint_eq(0x38, ctrl7);
113 cester_assert_uint_eq(0x18, ctrl8);
114 cester_assert_uint_eq(2, response1[0]);
115 cester_assert_uint_eq(1, responseSize1);
116 cester_assert_uint_eq(0x22, response2[0]);
117 cester_assert_uint_eq(1, responseSize2);
118 cester_assert_uint_eq(0x22, response3[0]);
119 cester_assert_uint_eq(1, responseSize3);
120 cester_assert_uint_eq(2, response4[0]);
121 cester_assert_uint_eq(1, responseSize4);
122 cester_assert_uint_ge(ackTime1, 500);
123 cester_assert_uint_lt(ackTime1, 7000);
124 cester_assert_uint_ge(ackTime2, 500);
125 cester_assert_uint_lt(ackTime2, 7000);
126 // Pausing at 1x is ~70ms
127 cester_assert_uint_ge(completeTime, 65000);
128 cester_assert_uint_eq(1, sector[0]);
129 cester_assert_uint_eq('C', sector[1]);
130 cester_assert_uint_eq('D', sector[2]);
131 cester_assert_uint_eq('0', sector[3]);
132 cester_assert_uint_eq('0', sector[4]);
133 cester_assert_uint_eq('1', sector[5]);
134 cester_assert_uint_eq(6, size);
135 ramsyscall_printf("Basic single 6 bytes readS @1x at 00:02:16, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime);
136)
137
138CESTER_TEST(cdlReadS1xwithDMA, test_instances,
139 int resetDone = resetCDRom();
140 if (!resetDone) {
141 cester_assert_true(resetDone);
142 return;
143 }
144
145 int setLocDone = setLoc(0, 2, 0x16);
146 if (!setLocDone) {
147 cester_assert_true(setLocDone);
148 return;
149 }
150
151 initializeTime();
152 CDROM_REG0 = 0;
153 CDROM_REG1 = CDL_READS;
154 uint32_t ackTime1 = waitCDRomIRQ();
155 uint8_t cause1 = ackCDRomCause();
156 uint8_t ctrl1 = CDROM_REG0 & ~3;
157 uint8_t response1[16];
158 uint8_t responseSize1 = readResponse(response1);
159 uint8_t ctrl2 = CDROM_REG0 & ~3;
160 CDROM_REG0 = 1;
161 uint8_t cause1b = CDROM_REG3_UC;
162
163 uint32_t readyTime = waitCDRomIRQ() - ackTime1;
164 uint8_t cause2 = ackCDRomCause();
165 uint8_t ctrl3 = CDROM_REG0 & ~3;
166 uint8_t response2[16];
167 uint8_t responseSize2 = readResponse(response2);
168 uint8_t ctrl4 = CDROM_REG0 & ~3;
169 CDROM_REG0 = 1;
170 uint8_t cause2b = CDROM_REG3_UC;
171
172 initializeTime();
173 uint8_t sector[2048];
174
175 CDROM_REG0 = 0;
176 CDROM_REG3 = 0x80;
177
178 uint32_t dicr = DICR;
179 dicr &= 0x00ffffff;
180 dicr |= 0x00880000;
181 DICR = dicr;
182 DPCR |= 0x8000;
183 DMA_CTRL[DMA_CDROM].MADR = (uintptr_t)sector;
184 DMA_CTRL[DMA_CDROM].BCR = (2048 >> 2) | 0x10000;
185 DMA_CTRL[DMA_CDROM].CHCR = 0x11000000;
186
187 while ((DMA_CTRL[DMA_CDROM].CHCR & 0x01000000) != 0);
188 dicr = DICR;
189 dicr &= 0x00ffffff;
190 dicr |= 0x88000000;
191 DICR = dicr;
192 CDROM_REG3 = 0;
193 uint32_t readTime = updateTime();
194
195 initializeTime();
196 CDROM_REG0 = 0;
197 CDROM_REG1 = CDL_PAUSE;
198 uint32_t ackTime2 = waitCDRomIRQ();
199 uint8_t cause3 = ackCDRomCause();
200 uint8_t ctrl5 = CDROM_REG0 & ~3;
201 uint8_t response3[16];
202 uint8_t responseSize3 = readResponse(response3);
203 uint8_t ctrl6 = CDROM_REG0 & ~3;
204 CDROM_REG0 = 1;
205 uint8_t cause3b = CDROM_REG3_UC;
206
207 uint32_t completeTime = waitCDRomIRQ() - ackTime2;
208 uint8_t cause4 = ackCDRomCause();
209 uint8_t ctrl7 = CDROM_REG0 & ~3;
210 uint8_t response4[16];
211 uint8_t responseSize4 = readResponse(response4);
212 uint8_t ctrl8 = CDROM_REG0 & ~3;
213 CDROM_REG0 = 1;
214 uint8_t cause4b = CDROM_REG3_UC;
215
216 cester_assert_uint_eq(3, cause1);
217 cester_assert_uint_eq(0xe0, cause1b);
218 cester_assert_uint_eq(1, cause2);
219 cester_assert_uint_eq(0xe0, cause2b);
220 cester_assert_uint_eq(3, cause3);
221 cester_assert_uint_eq(0xe0, cause3b);
222 cester_assert_uint_eq(2, cause4);
223 cester_assert_uint_eq(0xe0, cause4b);
224 cester_assert_uint_eq(0x38, ctrl1);
225 cester_assert_uint_eq(0x18, ctrl2);
226 cester_assert_uint_eq(0x38, ctrl3);
227 cester_assert_uint_eq(0x18, ctrl4);
228 cester_assert_uint_eq(0x38, ctrl5);
229 cester_assert_uint_eq(0x18, ctrl6);
230 cester_assert_uint_eq(0x38, ctrl7);
231 cester_assert_uint_eq(0x18, ctrl8);
232 cester_assert_uint_eq(2, response1[0]);
233 cester_assert_uint_eq(1, responseSize1);
234 cester_assert_uint_eq(0x22, response2[0]);
235 cester_assert_uint_eq(1, responseSize2);
236 cester_assert_uint_eq(0x22, response3[0]);
237 cester_assert_uint_eq(1, responseSize3);
238 cester_assert_uint_eq(2, response4[0]);
239 cester_assert_uint_eq(1, responseSize4);
240 cester_assert_uint_ge(ackTime1, 500);
241 cester_assert_uint_lt(ackTime1, 7000);
242 cester_assert_uint_ge(ackTime2, 500);
243 cester_assert_uint_lt(ackTime2, 7000);
244 // Pausing at 1x is ~70ms
245 cester_assert_uint_ge(completeTime, 65000);
246 cester_assert_uint_eq(1, sector[0]);
247 cester_assert_uint_eq('C', sector[1]);
248 cester_assert_uint_eq('D', sector[2]);
249 cester_assert_uint_eq('0', sector[3]);
250 cester_assert_uint_eq('0', sector[4]);
251 cester_assert_uint_eq('1', sector[5]);
252 ramsyscall_printf("Basic single full sector readS @1x with DMA at 00:02:16, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime);
253)
254
255CESTER_TEST(cdlReadS2x, test_instances,
256 int resetDone = resetCDRom();
257 if (!resetDone) {
258 cester_assert_true(resetDone);
259 return;
260 }
261
262 int setModeDone = setMode(0x80);
263 if (!setModeDone) {
264 cester_assert_true(setModeDone);
265 return;
266 }
267
268 int setLocDone = setLoc(0, 2, 0x16);
269 if (!setLocDone) {
270 cester_assert_true(setLocDone);
271 return;
272 }
273
274 initializeTime();
275 CDROM_REG0 = 0;
276 CDROM_REG1 = CDL_READS;
277 uint32_t ackTime1 = waitCDRomIRQ();
278 uint8_t cause1 = ackCDRomCause();
279 uint8_t ctrl1 = CDROM_REG0 & ~3;
280 uint8_t response1[16];
281 uint8_t responseSize1 = readResponse(response1);
282 uint8_t ctrl2 = CDROM_REG0 & ~3;
283 CDROM_REG0 = 1;
284 uint8_t cause1b = CDROM_REG3_UC;
285
286 uint32_t readyTime = waitCDRomIRQ() - ackTime1;
287 uint8_t cause2 = ackCDRomCause();
288 uint8_t ctrl3 = CDROM_REG0 & ~3;
289 uint8_t response2[16];
290 uint8_t responseSize2 = readResponse(response2);
291 uint8_t ctrl4 = CDROM_REG0 & ~3;
292 CDROM_REG0 = 1;
293 uint8_t cause2b = CDROM_REG3_UC;
294
295 initializeTime();
296 uint8_t sector[2048];
297 uint32_t size = 0;
298
299 CDROM_REG0 = 0;
300 CDROM_REG3 = 0x80;
301
302 while ((CDROM_REG0 & 0x40) == 0);
303 while (((CDROM_REG0 & 0x40) != 0) && (size < 6)) {
304 sector[size++] = CDROM_REG2;
305 }
306 CDROM_REG3 = 0;
307 uint32_t readTime = updateTime();
308
309 initializeTime();
310 CDROM_REG0 = 0;
311 CDROM_REG1 = CDL_PAUSE;
312 uint32_t ackTime2 = waitCDRomIRQ();
313 uint8_t cause3 = ackCDRomCause();
314 uint8_t ctrl5 = CDROM_REG0 & ~3;
315 uint8_t response3[16];
316 uint8_t responseSize3 = readResponse(response3);
317 uint8_t ctrl6 = CDROM_REG0 & ~3;
318 CDROM_REG0 = 1;
319 uint8_t cause3b = CDROM_REG3_UC;
320
321 uint32_t completeTime = waitCDRomIRQ() - ackTime2;
322 uint8_t cause4 = ackCDRomCause();
323 uint8_t ctrl7 = CDROM_REG0 & ~3;
324 uint8_t response4[16];
325 uint8_t responseSize4 = readResponse(response4);
326 uint8_t ctrl8 = CDROM_REG0 & ~3;
327 CDROM_REG0 = 1;
328 uint8_t cause4b = CDROM_REG3_UC;
329
330 cester_assert_uint_eq(3, cause1);
331 cester_assert_uint_eq(0xe0, cause1b);
332 cester_assert_uint_eq(1, cause2);
333 cester_assert_uint_eq(0xe0, cause2b);
334 cester_assert_uint_eq(3, cause3);
335 cester_assert_uint_eq(0xe0, cause3b);
336 cester_assert_uint_eq(2, cause4);
337 cester_assert_uint_eq(0xe0, cause4b);
338 cester_assert_uint_eq(0x38, ctrl1);
339 cester_assert_uint_eq(0x18, ctrl2);
340 cester_assert_uint_eq(0x38, ctrl3);
341 cester_assert_uint_eq(0x18, ctrl4);
342 cester_assert_uint_eq(0x38, ctrl5);
343 cester_assert_uint_eq(0x18, ctrl6);
344 cester_assert_uint_eq(0x38, ctrl7);
345 cester_assert_uint_eq(0x18, ctrl8);
346 cester_assert_uint_eq(2, response1[0]);
347 cester_assert_uint_eq(1, responseSize1);
348 cester_assert_uint_eq(0x22, response2[0]);
349 cester_assert_uint_eq(1, responseSize2);
350 cester_assert_uint_eq(0x22, response3[0]);
351 cester_assert_uint_eq(1, responseSize3);
352 cester_assert_uint_eq(2, response4[0]);
353 cester_assert_uint_eq(1, responseSize4);
354 cester_assert_uint_ge(ackTime1, 500);
355 cester_assert_uint_lt(ackTime1, 7000);
356 cester_assert_uint_ge(ackTime2, 500);
357 cester_assert_uint_lt(ackTime2, 7000);
358 // Switching speed is roughly 650ms for the speed up,
359 // and then this also contains the seeking time, and
360 // the time to read the first sector, which is 6.66ms
361 cester_assert_uint_ge(readyTime, 500000);
362 // Pausing at 2x is ~35ms
363 cester_assert_uint_ge(completeTime, 32500);
364 cester_assert_uint_eq(1, sector[0]);
365 cester_assert_uint_eq('C', sector[1]);
366 cester_assert_uint_eq('D', sector[2]);
367 cester_assert_uint_eq('0', sector[3]);
368 cester_assert_uint_eq('0', sector[4]);
369 cester_assert_uint_eq('1', sector[5]);
370 cester_assert_uint_eq(6, size);
371 ramsyscall_printf("Basic single 6 bytes readS @2x at 00:02:16, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime);
372)
373
374CESTER_TEST(cdlReadS2xwithDMA, test_instances,
375 int resetDone = resetCDRom();
376 if (!resetDone) {
377 cester_assert_true(resetDone);
378 return;
379 }
380
381 int setModeDone = setMode(0x80);
382 if (!setModeDone) {
383 cester_assert_true(setModeDone);
384 return;
385 }
386
387 int setLocDone = setLoc(0, 2, 0x16);
388 if (!setLocDone) {
389 cester_assert_true(setLocDone);
390 return;
391 }
392
393 initializeTime();
394 CDROM_REG0 = 0;
395 CDROM_REG1 = CDL_READS;
396 uint32_t ackTime1 = waitCDRomIRQ();
397 uint8_t cause1 = ackCDRomCause();
398 uint8_t ctrl1 = CDROM_REG0 & ~3;
399 uint8_t response1[16];
400 uint8_t responseSize1 = readResponse(response1);
401 uint8_t ctrl2 = CDROM_REG0 & ~3;
402 CDROM_REG0 = 1;
403 uint8_t cause1b = CDROM_REG3_UC;
404
405 uint32_t readyTime = waitCDRomIRQ() - ackTime1;
406 uint8_t cause2 = ackCDRomCause();
407 uint8_t ctrl3 = CDROM_REG0 & ~3;
408 uint8_t response2[16];
409 uint8_t responseSize2 = readResponse(response2);
410 uint8_t ctrl4 = CDROM_REG0 & ~3;
411 CDROM_REG0 = 1;
412 uint8_t cause2b = CDROM_REG3_UC;
413
414 initializeTime();
415 uint8_t sector[2048];
416
417 CDROM_REG0 = 0;
418 CDROM_REG3 = 0x80;
419
420 uint32_t dicr = DICR;
421 dicr &= 0x00ffffff;
422 dicr |= 0x00880000;
423 DICR = dicr;
424 DPCR |= 0x8000;
425 DMA_CTRL[DMA_CDROM].MADR = (uintptr_t)sector;
426 DMA_CTRL[DMA_CDROM].BCR = (2048 >> 2) | 0x10000;
427 DMA_CTRL[DMA_CDROM].CHCR = 0x11000000;
428
429 while ((DMA_CTRL[DMA_CDROM].CHCR & 0x01000000) != 0);
430 dicr = DICR;
431 dicr &= 0x00ffffff;
432 dicr |= 0x88000000;
433 DICR = dicr;
434 CDROM_REG3 = 0;
435 uint32_t readTime = updateTime();
436
437 initializeTime();
438 CDROM_REG0 = 0;
439 CDROM_REG1 = CDL_PAUSE;
440 uint32_t ackTime2 = waitCDRomIRQ();
441 uint8_t cause3 = ackCDRomCause();
442 uint8_t ctrl5 = CDROM_REG0 & ~3;
443 uint8_t response3[16];
444 uint8_t responseSize3 = readResponse(response3);
445 uint8_t ctrl6 = CDROM_REG0 & ~3;
446 CDROM_REG0 = 1;
447 uint8_t cause3b = CDROM_REG3_UC;
448
449 uint32_t completeTime = waitCDRomIRQ() - ackTime2;
450 uint8_t cause4 = ackCDRomCause();
451 uint8_t ctrl7 = CDROM_REG0 & ~3;
452 uint8_t response4[16];
453 uint8_t responseSize4 = readResponse(response4);
454 uint8_t ctrl8 = CDROM_REG0 & ~3;
455 CDROM_REG0 = 1;
456 uint8_t cause4b = CDROM_REG3_UC;
457
458 cester_assert_uint_eq(3, cause1);
459 cester_assert_uint_eq(0xe0, cause1b);
460 cester_assert_uint_eq(1, cause2);
461 cester_assert_uint_eq(0xe0, cause2b);
462 cester_assert_uint_eq(3, cause3);
463 cester_assert_uint_eq(0xe0, cause3b);
464 cester_assert_uint_eq(2, cause4);
465 cester_assert_uint_eq(0xe0, cause4b);
466 cester_assert_uint_eq(0x38, ctrl1);
467 cester_assert_uint_eq(0x18, ctrl2);
468 cester_assert_uint_eq(0x38, ctrl3);
469 cester_assert_uint_eq(0x18, ctrl4);
470 cester_assert_uint_eq(0x38, ctrl5);
471 cester_assert_uint_eq(0x18, ctrl6);
472 cester_assert_uint_eq(0x38, ctrl7);
473 cester_assert_uint_eq(0x18, ctrl8);
474 cester_assert_uint_eq(2, response1[0]);
475 cester_assert_uint_eq(1, responseSize1);
476 cester_assert_uint_eq(0x22, response2[0]);
477 cester_assert_uint_eq(1, responseSize2);
478 cester_assert_uint_eq(0x22, response3[0]);
479 cester_assert_uint_eq(1, responseSize3);
480 cester_assert_uint_eq(2, response4[0]);
481 cester_assert_uint_eq(1, responseSize4);
482 cester_assert_uint_ge(ackTime1, 500);
483 cester_assert_uint_lt(ackTime1, 7000);
484 cester_assert_uint_ge(ackTime2, 500);
485 cester_assert_uint_lt(ackTime2, 7000);
486 // Switching speed is roughly 650ms for the speed up,
487 // and then this also contains the seeking time, and
488 // the time to read the first sector, which is 6.66ms
489 cester_assert_uint_ge(readyTime, 500000);
490 // Pausing at 2x is ~35ms
491 cester_assert_uint_ge(completeTime, 32500);
492 cester_assert_uint_eq(1, sector[0]);
493 cester_assert_uint_eq('C', sector[1]);
494 cester_assert_uint_eq('D', sector[2]);
495 cester_assert_uint_eq('0', sector[3]);
496 cester_assert_uint_eq('0', sector[4]);
497 cester_assert_uint_eq('1', sector[5]);
498 ramsyscall_printf("Basic single full sector readS @2x with DMA at 00:02:16, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime);
499)
500
501CESTER_TEST(cdlReadS2xRunaway, test_instances,
502 int resetDone = resetCDRom();
503 if (!resetDone) {
504 cester_assert_true(resetDone);
505 return;
506 }
507
508 int setModeDone = setMode(0x80);
509 if (!setModeDone) {
510 cester_assert_true(setModeDone);
511 return;
512 }
513
514 int setLocDone = setLoc(0, 2, 0x16);
515 if (!setLocDone) {
516 cester_assert_true(setLocDone);
517 return;
518 }
519
520 initializeTime();
521 CDROM_REG0 = 0;
522 CDROM_REG1 = CDL_READS;
523 uint32_t ackTime1 = waitCDRomIRQ();
524 uint8_t cause1 = ackCDRomCause();
525 uint8_t ctrl1 = CDROM_REG0 & ~3;
526 uint8_t response1[16];
527 uint8_t responseSize1 = readResponse(response1);
528 uint8_t ctrl2 = CDROM_REG0 & ~3;
529 CDROM_REG0 = 1;
530 uint8_t cause1b = CDROM_REG3_UC;
531
532 uint32_t readyTime = waitCDRomIRQ() - ackTime1;
533 uint8_t cause2 = ackCDRomCause();
534 uint8_t ctrl3 = CDROM_REG0 & ~3;
535 uint8_t response2[16];
536 uint8_t responseSize2 = readResponse(response2);
537 uint8_t ctrl4 = CDROM_REG0 & ~3;
538 CDROM_REG0 = 1;
539 uint8_t cause2b = CDROM_REG3_UC;
540
541 initializeTime();
542 uint8_t sector[2048];
543 uint32_t size = 0;
544
545 CDROM_REG0 = 0;
546 CDROM_REG3 = 0x80;
547 while ((CDROM_REG0 & 0x40) == 0);
548 while (((CDROM_REG0 & 0x40) != 0) && (size < 6)) {
549 sector[size++] = CDROM_REG2;
550 }
551 uint32_t readTime = updateTime();
552
553 initializeTime();
554 CDROM_REG0 = 0;
555 CDROM_REG1 = CDL_PAUSE;
556 uint32_t ackTime2 = waitCDRomIRQ();
557 uint8_t cause3 = ackCDRomCause();
558 uint8_t ctrl5 = CDROM_REG0 & ~3;
559 uint8_t response3[16];
560 uint8_t responseSize3 = readResponse(response3);
561 uint8_t ctrl6 = CDROM_REG0 & ~3;
562 CDROM_REG0 = 1;
563 uint8_t cause3b = CDROM_REG3_UC;
564
565 uint32_t completeTime = waitCDRomIRQ() - ackTime2;
566 uint8_t cause4 = ackCDRomCause();
567 uint8_t ctrl7 = CDROM_REG0 & ~3;
568 uint8_t response4[16];
569 uint8_t responseSize4 = readResponse(response4);
570 uint8_t ctrl8 = CDROM_REG0 & ~3;
571 CDROM_REG0 = 1;
572 uint8_t cause4b = CDROM_REG3_UC;
573 CDROM_REG0 = 0;
574 CDROM_REG3 = 0;
575
576 cester_assert_uint_eq(3, cause1);
577 cester_assert_uint_eq(0xe0, cause1b);
578 cester_assert_uint_eq(1, cause2);
579 cester_assert_uint_eq(0xe0, cause2b);
580 cester_assert_uint_eq(3, cause3);
581 cester_assert_uint_eq(0xe0, cause3b);
582 cester_assert_uint_eq(2, cause4);
583 cester_assert_uint_eq(0xe0, cause4b);
584 cester_assert_uint_eq(0x38, ctrl1);
585 cester_assert_uint_eq(0x18, ctrl2);
586 cester_assert_uint_eq(0x38, ctrl3);
587 cester_assert_uint_eq(0x18, ctrl4);
588 cester_assert_uint_eq(0x78, ctrl5);
589 cester_assert_uint_eq(0x58, ctrl6);
590 cester_assert_uint_eq(0x78, ctrl7);
591 cester_assert_uint_eq(0x58, ctrl8);
592 cester_assert_uint_eq(2, response1[0]);
593 cester_assert_uint_eq(1, responseSize1);
594 cester_assert_uint_eq(0x22, response2[0]);
595 cester_assert_uint_eq(1, responseSize2);
596 cester_assert_uint_eq(0x22, response3[0]);
597 cester_assert_uint_eq(1, responseSize3);
598 cester_assert_uint_eq(2, response4[0]);
599 cester_assert_uint_eq(1, responseSize4);
600 cester_assert_uint_ge(ackTime1, 500);
601 cester_assert_uint_lt(ackTime1, 7000);
602 cester_assert_uint_ge(ackTime2, 500);
603 cester_assert_uint_lt(ackTime2, 7000);
604 // Switching speed is roughly 650ms for the speed up,
605 // and then this also contains the seeking time, and
606 // the time to read the first sector, which is 6.66ms
607 cester_assert_uint_ge(readyTime, 500000);
608 // Pausing at 2x is ~35ms
609 cester_assert_uint_ge(completeTime, 32500);
610 cester_assert_uint_eq(1, sector[0]);
611 cester_assert_uint_eq('C', sector[1]);
612 cester_assert_uint_eq('D', sector[2]);
613 cester_assert_uint_eq('0', sector[3]);
614 cester_assert_uint_eq('0', sector[4]);
615 cester_assert_uint_eq('1', sector[5]);
616 cester_assert_uint_eq(6, size);
617 ramsyscall_printf("Basic single 6 bytes readS @2x at 00:02:16, runaway read, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime);
618)
619
620CESTER_TEST(cdlReadSInAudio, test_instances,
621 int resetDone = resetCDRom();
622 if (!resetDone) {
623 cester_assert_true(resetDone);
624 return;
625 }
626
627 int setLocDone = setLoc(0x70, 0x21, 0);
628 if (!setLocDone) {
629 cester_assert_true(setLocDone);
630 return;
631 }
632
633 initializeTime();
634 CDROM_REG0 = 0;
635 CDROM_REG1 = CDL_READS;
636 uint32_t ackTime = waitCDRomIRQ();
637 uint8_t cause1 = ackCDRomCause();
638 uint8_t ctrl1 = CDROM_REG0 & ~3;
639 uint8_t response1[16];
640 uint8_t responseSize1 = readResponse(response1);
641 uint8_t ctrl2 = CDROM_REG0 & ~3;
642 CDROM_REG0 = 1;
643 uint8_t cause1b = CDROM_REG3_UC;
644
645 uint32_t errorTime = waitCDRomIRQ() - ackTime;
646 uint8_t cause2 = ackCDRomCause();
647 uint8_t ctrl3 = CDROM_REG0 & ~3;
648 uint8_t response2[16];
649 uint8_t responseSize2 = readResponse(response2);
650 uint8_t ctrl4 = CDROM_REG0 & ~3;
651 CDROM_REG0 = 1;
652 uint8_t cause2b = CDROM_REG3_UC;
653
654 cester_assert_uint_eq(3, cause1);
655 cester_assert_uint_eq(0xe0, cause1b);
656 cester_assert_uint_eq(5, cause2);
657 cester_assert_uint_eq(0xe0, cause2b);
658 cester_assert_uint_eq(0x38, ctrl1);
659 cester_assert_uint_eq(0x18, ctrl2);
660 cester_assert_uint_eq(0x38, ctrl3);
661 cester_assert_uint_eq(0x18, ctrl4);
662 cester_assert_uint_eq(2, response1[0]);
663 cester_assert_uint_eq(1, responseSize1);
664 cester_assert_uint_eq(6, response2[0]);
665 cester_assert_uint_eq(4, response2[1]);
666 cester_assert_uint_eq(2, responseSize2);
667 cester_assert_uint_ge(ackTime, 500);
668 cester_assert_uint_lt(ackTime, 7000);
669 cester_assert_uint_ge(errorTime, 4000000);
670 ramsyscall_printf("Basic readS in audio track, ack in %ius, errored in %ius\n", ackTime, errorTime);
671)
672
673CESTER_TEST(cdlReadSTooFar, test_instances,
674 int resetDone = resetCDRom();
675 if (!resetDone) {
676 cester_assert_true(resetDone);
677 return;
678 }
679
680 int setLocDone = setLoc(0x80, 0, 0);
681 if (!setLocDone) {
682 cester_assert_true(setLocDone);
683 return;
684 }
685
686 initializeTime();
687 CDROM_REG0 = 0;
688 CDROM_REG1 = CDL_READS;
689 uint32_t ackTime = waitCDRomIRQ();
690 uint8_t cause1 = ackCDRomCause();
691 uint8_t ctrl1 = CDROM_REG0 & ~3;
692 uint8_t response1[16];
693 uint8_t responseSize1 = readResponse(response1);
694 uint8_t ctrl2 = CDROM_REG0 & ~3;
695 CDROM_REG0 = 1;
696 uint8_t cause1b = CDROM_REG3_UC;
697
698 uint32_t errorTime = waitCDRomIRQ() - ackTime;
699 uint8_t cause2 = ackCDRomCause();
700 uint8_t ctrl3 = CDROM_REG0 & ~3;
701 uint8_t response2[16];
702 uint8_t responseSize2 = readResponse(response2);
703 uint8_t ctrl4 = CDROM_REG0 & ~3;
704 CDROM_REG0 = 1;
705 uint8_t cause2b = CDROM_REG3_UC;
706
707 cester_assert_uint_eq(3, cause1);
708 cester_assert_uint_eq(0xe0, cause1b);
709 cester_assert_uint_eq(5, cause2);
710 cester_assert_uint_eq(0xe0, cause2b);
711 cester_assert_uint_eq(0x38, ctrl1);
712 cester_assert_uint_eq(0x18, ctrl2);
713 cester_assert_uint_eq(0x38, ctrl3);
714 cester_assert_uint_eq(0x18, ctrl4);
715 cester_assert_uint_eq(2, response1[0]);
716 cester_assert_uint_eq(1, responseSize1);
717 cester_assert_uint_eq(6, response2[0]);
718 cester_assert_uint_eq(0x10, response2[1]);
719 cester_assert_uint_eq(2, responseSize2);
720 cester_assert_uint_ge(ackTime, 500);
721 cester_assert_uint_lt(ackTime, 7000);
722 cester_assert_uint_ge(errorTime, 600000);
723 ramsyscall_printf("Basic readS too far, ack in %ius, errored in %ius\n", ackTime, errorTime);
724)
725
726CESTER_TEST(cdlReadS2xWithNop, test_instances,
727 int resetDone = resetCDRom();
728 if (!resetDone) {
729 cester_assert_true(resetDone);
730 return;
731 }
732
733 int setModeDone = setMode(0x80);
734 if (!setModeDone) {
735 cester_assert_true(setModeDone);
736 return;
737 }
738
739 int setLocDone = setLoc(0x70, 0, 0);
740 if (!setLocDone) {
741 cester_assert_true(setLocDone);
742 return;
743 }
744
745 initializeTime();
746 CDROM_REG0 = 0;
747 CDROM_REG1 = CDL_READS;
748 uint32_t ackTime1 = waitCDRomIRQ();
749 uint8_t cause1 = ackCDRomCause();
750 uint8_t ctrl1 = CDROM_REG0 & ~3;
751 uint8_t response1[16];
752 uint8_t responseSize1 = readResponse(response1);
753 uint8_t ctrl2 = CDROM_REG0 & ~3;
754 CDROM_REG0 = 1;
755 uint8_t cause1b = CDROM_REG3_UC;
756
757 CDROM_REG0 = 0;
758 CDROM_REG1 = CDL_NOP;
759
760 uint8_t ctrl2b = CDROM_REG0 & ~3;
761
762 uint32_t ackTime2 = waitCDRomIRQ() - ackTime1;
763 uint8_t cause2 = ackCDRomCause();
764 uint8_t ctrl3 = CDROM_REG0 & ~3;
765 uint8_t response2[16];
766 uint8_t responseSize2 = readResponse(response2);
767 uint8_t ctrl4 = CDROM_REG0 & ~3;
768 CDROM_REG0 = 1;
769 uint8_t cause2b = CDROM_REG3_UC;
770
771 initializeTime();
772 uint32_t readyTime = waitCDRomIRQ();
773 uint8_t cause3 = ackCDRomCause();
774 uint8_t ctrl5 = CDROM_REG0 & ~3;
775 uint8_t response3[16];
776 uint8_t responseSize3 = readResponse(response3);
777 uint8_t ctrl6 = CDROM_REG0 & ~3;
778 CDROM_REG0 = 1;
779 uint8_t cause3b = CDROM_REG3_UC;
780
781 initializeTime();
782 CDROM_REG0 = 0;
783 CDROM_REG1 = CDL_PAUSE;
784 uint32_t ackTime3 = waitCDRomIRQ();
785 uint8_t cause4 = ackCDRomCause();
786 uint8_t ctrl7 = CDROM_REG0 & ~3;
787 uint8_t response4[16];
788 uint8_t responseSize4 = readResponse(response4);
789 uint8_t ctrl8 = CDROM_REG0 & ~3;
790 CDROM_REG0 = 1;
791 uint8_t cause4b = CDROM_REG3_UC;
792
793 uint32_t completeTime = waitCDRomIRQ() - ackTime3;
794 uint8_t cause5 = ackCDRomCause();
795 uint8_t ctrl9 = CDROM_REG0 & ~3;
796 uint8_t response5[16];
797 uint8_t responseSize5 = readResponse(response5);
798 uint8_t ctrl10 = CDROM_REG0 & ~3;
799 CDROM_REG0 = 1;
800 uint8_t cause5b = CDROM_REG3_UC;
801
802 cester_assert_uint_eq(3, cause1);
803 cester_assert_uint_eq(0xe0, cause1b);
804 cester_assert_uint_eq(3, cause2);
805 cester_assert_uint_eq(0xe0, cause2b);
806 cester_assert_uint_eq(1, cause3);
807 cester_assert_uint_eq(0xe0, cause3b);
808 cester_assert_uint_eq(3, cause4);
809 cester_assert_uint_eq(0xe0, cause4b);
810 cester_assert_uint_eq(2, cause5);
811 cester_assert_uint_eq(0xe0, cause5b);
812 cester_assert_uint_eq(0x38, ctrl1);
813 cester_assert_uint_eq(0x18, ctrl2);
814 cester_assert_uint_eq(0x98, ctrl2b);
815 cester_assert_uint_eq(0x38, ctrl3);
816 cester_assert_uint_eq(0x18, ctrl4);
817 cester_assert_uint_eq(0x38, ctrl5);
818 cester_assert_uint_eq(0x18, ctrl6);
819 cester_assert_uint_eq(0x38, ctrl7);
820 cester_assert_uint_eq(0x18, ctrl8);
821 cester_assert_uint_eq(0x38, ctrl9);
822 cester_assert_uint_eq(0x18, ctrl10);
823 cester_assert_uint_eq(2, response1[0]);
824 cester_assert_uint_eq(1, responseSize1);
825 cester_assert_uint_eq(2, response2[0]);
826 cester_assert_uint_eq(1, responseSize2);
827 cester_assert_uint_eq(0x22, response3[0]);
828 cester_assert_uint_eq(1, responseSize3);
829 cester_assert_uint_eq(0x22, response4[0]);
830 cester_assert_uint_eq(1, responseSize4);
831 cester_assert_uint_eq(2, response5[0]);
832 cester_assert_uint_eq(1, responseSize5);
833 cester_assert_uint_ge(ackTime1, 500);
834 cester_assert_uint_lt(ackTime1, 7000);
835 cester_assert_uint_ge(ackTime2, 500);
836 cester_assert_uint_lt(ackTime2, 7000);
837 cester_assert_uint_ge(ackTime3, 500);
838 cester_assert_uint_lt(ackTime3, 7000);
839 cester_assert_uint_ge(readyTime, 500000);
840 cester_assert_uint_ge(completeTime, 32500);
841 ramsyscall_printf("Basic single full sector readS @2x with DMA at 70:00:00 with nop interleaved, ack1 in %ius, ack2 in %ius, ready in %ius, ack3 in %ius, complete in %ius\n", ackTime1, ackTime2, readyTime, ackTime3, completeTime);
842)
waitCDRomIRQ
waitCDRomIRQ()
ctrl6
uint8_t ctrl6
Definition cdlreads.c:203
cester_assert_uint_eq
cester_assert_uint_eq(3, cause1)
response4
uint8_t response4[16]
Definition cdlreads.c:210
cause4
uint8_t cause4
Definition cdlreads.c:208
CDROM_REG0
CDROM_REG0
Definition cdlreads.c:152
setModeDone
int setModeDone
Definition cdlreads.c:381
ackTime
uint32_t ackTime
Definition cdlreads.c:636
ackTime3
uint32_t ackTime3
Definition cdlreads.c:784
response2
uint8_t response2[16]
Definition cdlreads.c:166
responseSize2
uint8_t responseSize2
Definition cdlreads.c:167
responseSize1
uint8_t responseSize1
Definition cdlreads.c:158
response5
uint8_t response5[16]
Definition cdlreads.c:796
ctrl7
uint8_t ctrl7
Definition cdlreads.c:209
cause5
uint8_t cause5
Definition cdlreads.c:794
setLocDone
int setLocDone
Definition cdlreads.c:145
cause4b
uint8_t cause4b
Definition cdlreads.c:214
CDROM_REG3
CDROM_REG3
Definition cdlreads.c:176
resetDone
int resetDone
Definition cdlreads.c:139
ctrl4
uint8_t ctrl4
Definition cdlreads.c:168
ctrl2b
uint8_t ctrl2b
Definition cdlreads.c:760
response1
uint8_t response1[16]
Definition cdlreads.c:157
sector
uint8_t sector[2048]
Definition cdlreads.c:173
dicr
uint32_t dicr
Definition cdlreads.c:178
ackTime1
uint32_t ackTime1
Definition cdlreads.c:154
test_instances
test_instances
Definition cdlreads.c:138
cause2b
uint8_t cause2b
Definition cdlreads.c:170
ctrl5
uint8_t ctrl5
Definition cdlreads.c:200
cester_assert_uint_lt
cester_assert_uint_lt(ackTime1, 7000)
ctrl10
uint8_t ctrl10
Definition cdlreads.c:798
readTime
uint32_t readTime
Definition cdlreads.c:193
completeTime
uint32_t completeTime
Definition cdlreads.c:207
cause5b
uint8_t cause5b
Definition cdlreads.c:800
ctrl8
uint8_t ctrl8
Definition cdlreads.c:212
ctrl2
uint8_t ctrl2
Definition cdlreads.c:159
cause1
uint8_t cause1
Definition cdlreads.c:155
DICR
DICR
Definition cdlreads.c:181
cause2
uint8_t cause2
Definition cdlreads.c:164
ackTime2
uint32_t ackTime2
Definition cdlreads.c:198
errorTime
uint32_t errorTime
Definition cdlreads.c:645
CHCR
DMA_CTRL[DMA_CDROM] CHCR
Definition cdlreads.c:185
response3
uint8_t response3[16]
Definition cdlreads.c:201
cause1b
uint8_t cause1b
Definition cdlreads.c:161
cester_assert_uint_ge
cester_assert_uint_ge(ackTime1, 500)
ctrl1
uint8_t ctrl1
Definition cdlreads.c:156
responseSize3
uint8_t responseSize3
Definition cdlreads.c:202
cause3b
uint8_t cause3b
Definition cdlreads.c:205
CESTER_TEST
CESTER_TEST(cdlReadS1x, test_instances, int resetDone=resetCDRom();if(!resetDone) { cester_assert_true(resetDone);return;} int setLocDone=setLoc(0, 2, 0x16);if(!setLocDone) { cester_assert_true(setLocDone);return;} initializeTime();CDROM_REG0=0;CDROM_REG1=CDL_READS;uint32_t ackTime1=waitCDRomIRQ();uint8_t cause1=ackCDRomCause();uint8_t ctrl1=CDROM_REG0 &~3;uint8_t response1[16];uint8_t responseSize1=readResponse(response1);uint8_t ctrl2=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause1b=CDROM_REG3_UC;uint32_t readyTime=waitCDRomIRQ() - ackTime1;uint8_t cause2=ackCDRomCause();uint8_t ctrl3=CDROM_REG0 &~3;uint8_t response2[16];uint8_t responseSize2=readResponse(response2);uint8_t ctrl4=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause2b=CDROM_REG3_UC;initializeTime();uint8_t sector[2048];uint32_t size=0;CDROM_REG0=0;CDROM_REG3=0x80;while((CDROM_REG0 &0x40)==0);while(((CDROM_REG0 &0x40) !=0) &&(size< 6)) { sector[size++]=CDROM_REG2;} CDROM_REG3=0;uint32_t readTime=updateTime();initializeTime();CDROM_REG0=0;CDROM_REG1=CDL_PAUSE;uint32_t ackTime2=waitCDRomIRQ();uint8_t cause3=ackCDRomCause();uint8_t ctrl5=CDROM_REG0 &~3;uint8_t response3[16];uint8_t responseSize3=readResponse(response3);uint8_t ctrl6=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause3b=CDROM_REG3_UC;uint32_t completeTime=waitCDRomIRQ() - ackTime2;uint8_t cause4=ackCDRomCause();uint8_t ctrl7=CDROM_REG0 &~3;uint8_t response4[16];uint8_t responseSize4=readResponse(response4);uint8_t ctrl8=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause4b=CDROM_REG3_UC;cester_assert_uint_eq(3, cause1);cester_assert_uint_eq(0xe0, cause1b);cester_assert_uint_eq(1, cause2);cester_assert_uint_eq(0xe0, cause2b);cester_assert_uint_eq(3, cause3);cester_assert_uint_eq(0xe0, cause3b);cester_assert_uint_eq(2, cause4);cester_assert_uint_eq(0xe0, cause4b);cester_assert_uint_eq(0x38, ctrl1);cester_assert_uint_eq(0x18, ctrl2);cester_assert_uint_eq(0x38, ctrl3);cester_assert_uint_eq(0x18, ctrl4);cester_assert_uint_eq(0x38, ctrl5);cester_assert_uint_eq(0x18, ctrl6);cester_assert_uint_eq(0x38, ctrl7);cester_assert_uint_eq(0x18, ctrl8);cester_assert_uint_eq(2, response1[0]);cester_assert_uint_eq(1, responseSize1);cester_assert_uint_eq(0x22, response2[0]);cester_assert_uint_eq(1, responseSize2);cester_assert_uint_eq(0x22, response3[0]);cester_assert_uint_eq(1, responseSize3);cester_assert_uint_eq(2, response4[0]);cester_assert_uint_eq(1, responseSize4);cester_assert_uint_ge(ackTime1, 500);cester_assert_uint_lt(ackTime1, 7000);cester_assert_uint_ge(ackTime2, 500);cester_assert_uint_lt(ackTime2, 7000);cester_assert_uint_ge(completeTime, 65000);cester_assert_uint_eq(1, sector[0]);cester_assert_uint_eq('C', sector[1]);cester_assert_uint_eq('D', sector[2]);cester_assert_uint_eq('0', sector[3]);cester_assert_uint_eq('0', sector[4]);cester_assert_uint_eq('1', sector[5]);cester_assert_uint_eq(6, size);ramsyscall_printf("Basic single 6 bytes readS @1x at 00:02:16, ack1 in %ius, ready in %ius, read in %ius, ack2 in %ius, complete in %ius\n", ackTime1, readyTime, readTime, ackTime2, completeTime);) CESTER_TEST(cdlReadS1xwithDMA
DPCR
DPCR
Definition cdlreads.c:182
initializeTime
initializeTime()
CDROM_REG1
CDROM_REG1
Definition cdlreads.c:153
readyTime
uint32_t readyTime
Definition cdlreads.c:163
ctrl9
uint8_t ctrl9
Definition cdlreads.c:795
ctrl3
uint8_t ctrl3
Definition cdlreads.c:165
cause3
uint8_t cause3
Definition cdlreads.c:199
responseSize5
uint8_t responseSize5
Definition cdlreads.c:797
responseSize4
uint8_t responseSize4
Definition cdlreads.c:211
CDL_READS
@ CDL_READS
Definition cdrom.h:69
CDL_NOP
@ CDL_NOP
Definition cdrom.h:43
CDL_PAUSE
@ CDL_PAUSE
Definition cdrom.h:51
CDROM_REG3_UC
#define CDROM_REG3_UC
Definition cdrom.h:39
CDROM_REG2
#define CDROM_REG2
Definition cdrom.h:33
size
static int size
Definition string.h:142
ramsyscall_printf
ramsyscall_printf("=== e01_kseg1_reads_no_fill ===\n")
DMA_CTRL
#define DMA_CTRL
Definition dma.h:36
DMA_CDROM
@ DMA_CDROM
Definition dma.h:42
ackCDRomCause
ackCDRomCause()
cester_assert_true
cester_assert_true(seekDone)
readResponse
readResponse(response)
uint32_t
void uint32_t(classId, spec)
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