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Bare-metal libraries and examples for the original PlayStation
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Classes | Macros
gte-latency-common.h File Reference
#include "common/hardware/cop2.h"
#include "common/syscalls/syscalls.h"
Include dependency graph for gte-latency-common.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct  probe_result_t
 

Macros

#define MAX_N   32
 
#define PROBE_DATA_AT_OFFSET(N, op_imm, dst_reg, canary)
 
#define PROBE_DATA_BASELINE(op_imm, dst_reg, canary)
 
#define PROBE_DATA_SANITY_PRE(op_imm, dst_reg, canary)
 
#define PROBE_CTRL_AT_OFFSET(N, op_imm, dst_reg, canary)
 
#define PROBE_CTRL_BASELINE(op_imm, dst_reg, canary)
 
#define PROBE_CTRL_SANITY_PRE(op_imm, dst_reg, canary)
 
#define DO_SWEEP_DATA(setup_fn, op_imm, dst_reg, canary, results)
 
#define DO_SWEEP_CTRL(setup_fn, op_imm, dst_reg, canary, results)
 
#define MAKE_DATA_TEST(test_name, scene_setup, op_imm, dst_reg, canary, label)
 
#define MAKE_CTRL_TEST(test_name, scene_setup, op_imm, dst_reg, canary, label)
 

Macro Definition Documentation

◆ DO_SWEEP_CTRL

#define DO_SWEEP_CTRL (   setup_fn,
  op_imm,
  dst_reg,
  canary,
  results 
)

◆ DO_SWEEP_DATA

#define DO_SWEEP_DATA (   setup_fn,
  op_imm,
  dst_reg,
  canary,
  results 
)

◆ MAKE_CTRL_TEST

#define MAKE_CTRL_TEST (   test_name,
  scene_setup,
  op_imm,
  dst_reg,
  canary,
  label 
)
Value:
CESTER_TEST(test_name, gte_latency_tests, \
static probe_result_t baseline, sanity_pre; \
static probe_result_t warmup[MAX_N + 1]; \
static probe_result_t results[MAX_N + 1]; \
scene_setup(); \
PROBE_CTRL_BASELINE(op_imm, dst_reg, canary); \
read_full_state(&baseline); \
scene_setup(); \
PROBE_CTRL_SANITY_PRE(op_imm, dst_reg, canary); \
read_full_state(&sanity_pre); \
uint32_t saved_sr = irq_disable(); \
DO_SWEEP_CTRL(scene_setup, op_imm, dst_reg, canary, warmup); \
DO_SWEEP_CTRL(scene_setup, op_imm, dst_reg, canary, results); \
irq_restore(saved_sr); \
report_sweep(label, &baseline, &sanity_pre, results); \
cester_assert_true(!results_equal(&baseline, &sanity_pre)); \
)
CESTER_TEST
CESTER_TEST(cddaLevelHalf, test_instances, static const uint8_t atv[4]={0x40, 0x00, 0x40, 0x00};unsigned changes=0;int peak=cddaPeak(atv, 1, &changes);ramsyscall_printf("CD-DA level at half ATV: peak %i, %u sign changes\n", peak, changes);cester_assert_int_ge(peak, 11300);cester_assert_int_le(peak, 11800);cester_assert_uint_ge(changes, 4);) CESTER_TEST(cddaLevelClipped
MAX_N
#define MAX_N
Definition gte-latency-common.h:51
probe_result_t
Definition gte-latency-common.h:60

◆ MAKE_DATA_TEST

#define MAKE_DATA_TEST (   test_name,
  scene_setup,
  op_imm,
  dst_reg,
  canary,
  label 
)
Value:
CESTER_TEST(test_name, gte_latency_tests, \
static probe_result_t baseline, sanity_pre; \
static probe_result_t warmup[MAX_N + 1]; \
static probe_result_t results[MAX_N + 1]; \
scene_setup(); \
PROBE_DATA_BASELINE(op_imm, dst_reg, canary); \
read_full_state(&baseline); \
scene_setup(); \
PROBE_DATA_SANITY_PRE(op_imm, dst_reg, canary); \
read_full_state(&sanity_pre); \
uint32_t saved_sr = irq_disable(); \
DO_SWEEP_DATA(scene_setup, op_imm, dst_reg, canary, warmup); \
DO_SWEEP_DATA(scene_setup, op_imm, dst_reg, canary, results); \
irq_restore(saved_sr); \
report_sweep(label, &baseline, &sanity_pre, results); \
cester_assert_true(!results_equal(&baseline, &sanity_pre)); \
)

◆ MAX_N

#define MAX_N   32

◆ PROBE_CTRL_AT_OFFSET

#define PROBE_CTRL_AT_OFFSET (   N,
  op_imm,
  dst_reg,
  canary 
)
Value:
do { \
__asm__ volatile( \
"cop2 %0\n\t" \
".rept " #N "\n\t" \
"nop\n\t" \
".endr\n\t" \
"ctc2 %1, $" #dst_reg "\n\t" \
".rept 60\n\t" \
"nop\n\t" \
".endr\n\t" \
: \
: "i"(op_imm), "r"((uint32_t)(canary)) \
: "memory"); \
} while (0)
N
#define N
Definition main.c:37
__asm__
__asm__(" .section .text.monitorSlotEntry, \"ax\", @progbits\n" " .align 2\n" " .global monitorSlotEntry\n" " .type monitorSlotEntry, @function\n" " .set push\n" " .set noreorder\n" " .set noat\n" "monitorSlotEntry:\n" " mfc0 $v0, $13\n" " nop\n" " andi $v0, $v0, 0x7c\n" " beqz $v0, 1f\n" " srl $v0, $v0, 2\n" " li $v1, " MON_STR(MON_SLOT_EXCMASK) "\n" " srlv $v1, $v1, $v0\n" " andi $v1, $v1, 1\n" " bnez $v1, 2f\n" " nop\n" " jr $ra\n" " nop\n" "1:\n" MON_SLOT_RX_TEST " jr $ra\n" " nop\n" "2:\n" " sw $a0, 0x10($k0)\n" " sw $a1, 0x14($k0)\n" " sw $a2, 0x18($k0)\n" " sw $a3, 0x1c($k0)\n" " mfc0 $a0, $12\n" " nop\n" " sw $a0, 0x8c($k0)\n" " mfc0 $a1, $13\n" " nop\n" " sw $a1, 0x90($k0)\n" " sw $k1, 0x6c($k0)\n" " sw $s0, 0x40($k0)\n" " sw $s1, 0x44($k0)\n" " sw $s2, 0x48($k0)\n" " sw $s3, 0x4c($k0)\n" " sw $s4, 0x50($k0)\n" " sw $s5, 0x54($k0)\n" " sw $s6, 0x58($k0)\n" " sw $s7, 0x5c($k0)\n" " sw $t0, 0x20($k0)\n" " sw $t1, 0x24($k0)\n" " sw $t2, 0x28($k0)\n" " sw $t3, 0x2c($k0)\n" " sw $t4, 0x30($k0)\n" " sw $t5, 0x34($k0)\n" " sw $t6, 0x38($k0)\n" " sw $t7, 0x3c($k0)\n" " sw $t8, 0x60($k0)\n" " sw $t9, 0x64($k0)\n" " sw $gp, 0x70($k0)\n" " sw $sp, 0x74($k0)\n" " sw $fp, 0x78($k0)\n" " mfhi $a0\n" " nop\n" " sw $a0, 0x84($k0)\n" " mflo $a0\n" " nop\n" " sw $a0, 0x88($k0)\n" " move $s0, $ra\n" " la $sp, monitorSlotStack + " MON_STR(MONITOR_SLOT_STACK_WORDS) " * 4 - 16\n" " jal monitorSlotDispatch\n" " nop\n" " lw $k0, 0x108($zero)\n" " move $ra, $s0\n" " lw $k0, 0($k0)\n" " nop\n" " addiu $k0, $k0, 8\n" " lw $a0, 0x84($k0)\n" " lw $a1, 0x88($k0)\n" " mthi $a0\n" " mtlo $a1\n" " lw $a0, 0x10($k0)\n" " lw $a1, 0x14($k0)\n" " lw $a2, 0x18($k0)\n" " lw $a3, 0x1c($k0)\n" " lw $t0, 0x20($k0)\n" " lw $t1, 0x24($k0)\n" " lw $t2, 0x28($k0)\n" " lw $t3, 0x2c($k0)\n" " lw $t4, 0x30($k0)\n" " lw $t5, 0x34($k0)\n" " lw $t6, 0x38($k0)\n" " lw $t7, 0x3c($k0)\n" " lw $t8, 0x60($k0)\n" " lw $t9, 0x64($k0)\n" " lw $s0, 0x40($k0)\n" " lw $sp, 0x74($k0)\n" " jr $ra\n" " nop\n" " .set pop\n" " .size monitorSlotEntry, . - monitorSlotEntry\n" " .previous\n")

◆ PROBE_CTRL_BASELINE

#define PROBE_CTRL_BASELINE (   op_imm,
  dst_reg,
  canary 
)
Value:
do { \
__asm__ volatile( \
"cop2 %0\n\t" \
".rept 80\n\t" \
"nop\n\t" \
".endr\n\t" \
"ctc2 %1, $" #dst_reg "\n\t" \
".rept 4\n\t" \
"nop\n\t" \
".endr\n\t" \
: \
: "i"(op_imm), "r"((uint32_t)(canary)) \
: "memory"); \
} while (0)

◆ PROBE_CTRL_SANITY_PRE

#define PROBE_CTRL_SANITY_PRE (   op_imm,
  dst_reg,
  canary 
)
Value:
do { \
__asm__ volatile( \
"ctc2 %1, $" #dst_reg "\n\t" \
"nop\n\tnop\n\t" \
"cop2 %0\n\t" \
".rept 80\n\t" \
"nop\n\t" \
".endr\n\t" \
: \
: "i"(op_imm), "r"((uint32_t)(canary)) \
: "memory"); \
} while (0)

◆ PROBE_DATA_AT_OFFSET

#define PROBE_DATA_AT_OFFSET (   N,
  op_imm,
  dst_reg,
  canary 
)
Value:
do { \
__asm__ volatile( \
"cop2 %0\n\t" \
".rept " #N "\n\t" \
"nop\n\t" \
".endr\n\t" \
"mtc2 %1, $" #dst_reg "\n\t" \
".rept 60\n\t" \
"nop\n\t" \
".endr\n\t" \
: \
: "i"(op_imm), "r"((uint32_t)(canary)) \
: "memory"); \
} while (0)

◆ PROBE_DATA_BASELINE

#define PROBE_DATA_BASELINE (   op_imm,
  dst_reg,
  canary 
)
Value:
do { \
__asm__ volatile( \
"cop2 %0\n\t" \
".rept 80\n\t" \
"nop\n\t" \
".endr\n\t" \
"mtc2 %1, $" #dst_reg "\n\t" \
".rept 4\n\t" \
"nop\n\t" \
".endr\n\t" \
: \
: "i"(op_imm), "r"((uint32_t)(canary)) \
: "memory"); \
} while (0)

◆ PROBE_DATA_SANITY_PRE

#define PROBE_DATA_SANITY_PRE (   op_imm,
  dst_reg,
  canary 
)
Value:
do { \
__asm__ volatile( \
"mtc2 %1, $" #dst_reg "\n\t" \
"nop\n\tnop\n\t" \
"cop2 %0\n\t" \
".rept 80\n\t" \
"nop\n\t" \
".endr\n\t" \
: \
: "i"(op_imm), "r"((uint32_t)(canary)) \
: "memory"); \
} while (0)
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