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gte-latency-common.h File Reference
#include "common/hardware/cop2.h"
#include "common/syscalls/syscalls.h"
Include dependency graph for gte-latency-common.h:
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Go to the source code of this file.

Classes

struct  probe_result_t
 

Macros

#define MAX_N   32
 
#define PROBE_DATA_AT_OFFSET(N, op_imm, dst_reg, canary)
 
#define PROBE_DATA_BASELINE(op_imm, dst_reg, canary)
 
#define PROBE_DATA_SANITY_PRE(op_imm, dst_reg, canary)
 
#define PROBE_CTRL_AT_OFFSET(N, op_imm, dst_reg, canary)
 
#define PROBE_CTRL_BASELINE(op_imm, dst_reg, canary)
 
#define PROBE_CTRL_SANITY_PRE(op_imm, dst_reg, canary)
 
#define DO_SWEEP_DATA(setup_fn, op_imm, dst_reg, canary, results)
 
#define DO_SWEEP_CTRL(setup_fn, op_imm, dst_reg, canary, results)
 
#define MAKE_DATA_TEST(test_name, scene_setup, op_imm, dst_reg, canary, label)
 
#define MAKE_CTRL_TEST(test_name, scene_setup, op_imm, dst_reg, canary, label)
 

Macro Definition Documentation

◆ DO_SWEEP_CTRL

#define DO_SWEEP_CTRL (   setup_fn,
  op_imm,
  dst_reg,
  canary,
  results 
)

◆ DO_SWEEP_DATA

#define DO_SWEEP_DATA (   setup_fn,
  op_imm,
  dst_reg,
  canary,
  results 
)

◆ MAKE_CTRL_TEST

#define MAKE_CTRL_TEST (   test_name,
  scene_setup,
  op_imm,
  dst_reg,
  canary,
  label 
)
Value:
CESTER_TEST(test_name, gte_latency_tests, \
static probe_result_t baseline, sanity_pre; \
static probe_result_t warmup[MAX_N + 1]; \
static probe_result_t results[MAX_N + 1]; \
scene_setup(); \
PROBE_CTRL_BASELINE(op_imm, dst_reg, canary); \
read_full_state(&baseline); \
scene_setup(); \
PROBE_CTRL_SANITY_PRE(op_imm, dst_reg, canary); \
read_full_state(&sanity_pre); \
uint32_t saved_sr = irq_disable(); \
DO_SWEEP_CTRL(scene_setup, op_imm, dst_reg, canary, warmup); \
DO_SWEEP_CTRL(scene_setup, op_imm, dst_reg, canary, results); \
irq_restore(saved_sr); \
report_sweep(label, &baseline, &sanity_pre, results); \
cester_assert_true(!results_equal(&baseline, &sanity_pre)); \
)
CESTER_TEST
CESTER_TEST(cpu_cop0_basic_write_bp, cpu_tests, uint32_t expectedEPC;uint32_t t;volatile uint32_t *ptr=(volatile uint32_t *) 0x58; *ptr=1;__asm__ volatile("" " lui %0, 0b1100101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0xfffffff0\n" " mtc0 %0, $9\n" :"=r"(t));cester_assert_uint_eq(1, *ptr);__asm__ volatile("la %0, 1f\n1:\nsw $0, 0x58($0)" :"=r"(expectedEPC));__asm__ volatile("mtc0 $0, $7\n");cester_assert_uint_eq(0, *ptr);cester_assert_uint_eq(1, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0x40, s_from);cester_assert_uint_eq(expectedEPC, s_epc);) CESTER_TEST(cpu_cop0_kseg_write_bp
MAX_N
#define MAX_N
Definition gte-latency-common.h:51
probe_result_t
Definition gte-latency-common.h:60
uint32_t
void uint32_t(classId, spec)

◆ MAKE_DATA_TEST

#define MAKE_DATA_TEST (   test_name,
  scene_setup,
  op_imm,
  dst_reg,
  canary,
  label 
)
Value:
CESTER_TEST(test_name, gte_latency_tests, \
static probe_result_t baseline, sanity_pre; \
static probe_result_t warmup[MAX_N + 1]; \
static probe_result_t results[MAX_N + 1]; \
scene_setup(); \
PROBE_DATA_BASELINE(op_imm, dst_reg, canary); \
read_full_state(&baseline); \
scene_setup(); \
PROBE_DATA_SANITY_PRE(op_imm, dst_reg, canary); \
read_full_state(&sanity_pre); \
uint32_t saved_sr = irq_disable(); \
DO_SWEEP_DATA(scene_setup, op_imm, dst_reg, canary, warmup); \
DO_SWEEP_DATA(scene_setup, op_imm, dst_reg, canary, results); \
irq_restore(saved_sr); \
report_sweep(label, &baseline, &sanity_pre, results); \
cester_assert_true(!results_equal(&baseline, &sanity_pre)); \
)

◆ MAX_N

#define MAX_N   32

◆ PROBE_CTRL_AT_OFFSET

#define PROBE_CTRL_AT_OFFSET (   N,
  op_imm,
  dst_reg,
  canary 
)
Value:
do { \
__asm__ volatile( \
"cop2 %0\n\t" \
".rept " #N "\n\t" \
"nop\n\t" \
".endr\n\t" \
"ctc2 %1, $" #dst_reg "\n\t" \
".rept 60\n\t" \
"nop\n\t" \
".endr\n\t" \
: \
: "i"(op_imm), "r"((uint32_t)(canary)) \
: "memory"); \
} while (0)

◆ PROBE_CTRL_BASELINE

#define PROBE_CTRL_BASELINE (   op_imm,
  dst_reg,
  canary 
)
Value:
do { \
__asm__ volatile( \
"cop2 %0\n\t" \
".rept 80\n\t" \
"nop\n\t" \
".endr\n\t" \
"ctc2 %1, $" #dst_reg "\n\t" \
".rept 4\n\t" \
"nop\n\t" \
".endr\n\t" \
: \
: "i"(op_imm), "r"((uint32_t)(canary)) \
: "memory"); \
} while (0)

◆ PROBE_CTRL_SANITY_PRE

#define PROBE_CTRL_SANITY_PRE (   op_imm,
  dst_reg,
  canary 
)
Value:
do { \
__asm__ volatile( \
"ctc2 %1, $" #dst_reg "\n\t" \
"nop\n\tnop\n\t" \
"cop2 %0\n\t" \
".rept 80\n\t" \
"nop\n\t" \
".endr\n\t" \
: \
: "i"(op_imm), "r"((uint32_t)(canary)) \
: "memory"); \
} while (0)

◆ PROBE_DATA_AT_OFFSET

#define PROBE_DATA_AT_OFFSET (   N,
  op_imm,
  dst_reg,
  canary 
)
Value:
do { \
__asm__ volatile( \
"cop2 %0\n\t" \
".rept " #N "\n\t" \
"nop\n\t" \
".endr\n\t" \
"mtc2 %1, $" #dst_reg "\n\t" \
".rept 60\n\t" \
"nop\n\t" \
".endr\n\t" \
: \
: "i"(op_imm), "r"((uint32_t)(canary)) \
: "memory"); \
} while (0)

◆ PROBE_DATA_BASELINE

#define PROBE_DATA_BASELINE (   op_imm,
  dst_reg,
  canary 
)
Value:
do { \
__asm__ volatile( \
"cop2 %0\n\t" \
".rept 80\n\t" \
"nop\n\t" \
".endr\n\t" \
"mtc2 %1, $" #dst_reg "\n\t" \
".rept 4\n\t" \
"nop\n\t" \
".endr\n\t" \
: \
: "i"(op_imm), "r"((uint32_t)(canary)) \
: "memory"); \
} while (0)

◆ PROBE_DATA_SANITY_PRE

#define PROBE_DATA_SANITY_PRE (   op_imm,
  dst_reg,
  canary 
)
Value:
do { \
__asm__ volatile( \
"mtc2 %1, $" #dst_reg "\n\t" \
"nop\n\tnop\n\t" \
"cop2 %0\n\t" \
".rept 80\n\t" \
"nop\n\t" \
".endr\n\t" \
: \
: "i"(op_imm), "r"((uint32_t)(canary)) \
: "memory"); \
} while (0)
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