40static void rasterDrawLineH(
void) {
42 rasterClearTestRegion(0, 0, 16, 16);
44 rasterFlushPrimitive();
48static void rasterDrawLineV(
void) {
50 rasterClearTestRegion(0, 0, 16, 16);
52 rasterFlushPrimitive();
56static void rasterDrawLineD45(
void) {
58 rasterClearTestRegion(0, 0, 16, 16);
60 rasterFlushPrimitive();
64static void rasterDrawLineDN45(
void) {
66 rasterClearTestRegion(0, 0, 16, 16);
68 rasterFlushPrimitive();
72static void rasterDrawLineZero(
void) {
74 rasterClearTestRegion(16, 16, 16, 8);
76 rasterFlushPrimitive();
81static void rasterDrawLineShallow(
void) {
83 rasterClearTestRegion(0, 0, 16, 8);
85 rasterFlushPrimitive();
94CESTER_TEST(lineH_before_start_pixel_4_10, gpu_raster_phase2,
99CESTER_TEST(lineH_start_pixel_5_10, gpu_raster_phase2,
104CESTER_TEST(lineH_interior_pixel_7_10, gpu_raster_phase2,
109CESTER_TEST(lineH_end_pixel_10_10_inclusive, gpu_raster_phase2,
114CESTER_TEST(lineH_past_end_pixel_11_10, gpu_raster_phase2,
119CESTER_TEST(lineH_below_line_pixel_5_11, gpu_raster_phase2,
128CESTER_TEST(lineV_before_start_pixel_10_4, gpu_raster_phase2,
133CESTER_TEST(lineV_start_pixel_10_5, gpu_raster_phase2,
138CESTER_TEST(lineV_interior_pixel_10_7, gpu_raster_phase2,
143CESTER_TEST(lineV_end_pixel_10_10_inclusive, gpu_raster_phase2,
148CESTER_TEST(lineV_past_end_pixel_10_11, gpu_raster_phase2,
157CESTER_TEST(lineD45_start_pixel_5_5, gpu_raster_phase2,
162CESTER_TEST(lineD45_interior_pixel_7_7, gpu_raster_phase2,
167CESTER_TEST(lineD45_end_pixel_10_10, gpu_raster_phase2,
172CESTER_TEST(lineD45_off_diag_pixel_5_6, gpu_raster_phase2,
177CESTER_TEST(lineD45_off_diag_pixel_6_5, gpu_raster_phase2,
186CESTER_TEST(lineDN45_start_pixel_5_10, gpu_raster_phase2,
187 rasterDrawLineDN45();
191CESTER_TEST(lineDN45_interior_pixel_7_8, gpu_raster_phase2,
192 rasterDrawLineDN45();
196CESTER_TEST(lineDN45_end_pixel_10_5, gpu_raster_phase2,
197 rasterDrawLineDN45();
205CESTER_TEST(lineZero_start_pixel_20_20, gpu_raster_phase2,
206 rasterDrawLineZero();
210CESTER_TEST(lineZero_neighbor_pixel_21_20, gpu_raster_phase2,
211 rasterDrawLineZero();
219CESTER_TEST(lineShallow_start_pixel_0_0, gpu_raster_phase2,
220 rasterDrawLineShallow();
224CESTER_TEST(lineShallow_midpoint_pixel_5_2, gpu_raster_phase2,
225 rasterDrawLineShallow();
229CESTER_TEST(lineShallow_end_pixel_10_3, gpu_raster_phase2,
230 rasterDrawLineShallow();
234CESTER_TEST(lineShallow_x_2_y_0_bresenham_choice, gpu_raster_phase2,
235 rasterDrawLineShallow();
CESTER_TEST(cddaLevelHalf, test_instances, static const uint8_t atv[4]={0x40, 0x00, 0x40, 0x00};unsigned changes=0;int peak=cddaPeak(atv, 1, &changes);ramsyscall_printf("CD-DA level at half ATV: peak %i, %u sign changes\n", peak, changes);cester_assert_int_ge(peak, 11300);cester_assert_int_le(peak, 11800);cester_assert_uint_ge(changes, 4);) CESTER_TEST(cddaLevelClipped
CESTER_BODY(static uint16_t s_cddaCapture;static int cddaSpuDma(uint32_t spuAddr, void *buf, uint32_t bytes, int isRead) { const uint16_t tsa=spuAddr > > 3;const uint16_t mode=isRead ? 0x30 :0x20;SPU_RAM_DTA=tsa;for(int i=0;i< 0xf01 &&SPU_RAM_DTA !=tsa;i++);SPU_CTRL=(SPU_CTRL &~0x30)|mode;for(volatile int i=0;i< 60;i++);for(int i=0;i< 0xf01 &&(SPU_STATUS &0x30) !=mode;i++);CDDA_SPU_DELAY=(CDDA_SPU_DELAY &0xf0ffffff)|(isRead ? 0x22000000 :0x20000000);DMA_CTRL[DMA_SPU].MADR=(uint32_t) buf &0x1fffffff;DMA_CTRL[DMA_SPU].BCR=((bytes > > 6)<< 16)|0x10;DMA_CTRL[DMA_SPU].CHCR=isRead ? 0x01000200 :0x01000201;int ok=0;for(unsigned t=0;t< 4000000u;t++) { if((DMA_CTRL[DMA_SPU].CHCR &0x01000000)==0) { ok=1;break;} } SPU_CTRL=SPU_CTRL &~0x30;for(volatile int i=0;i< 60;i++);return ok;} static int cddaSimpleCmd(uint8_t cmd) { uint8_t response[16];CDROM_REG0=0;CDROM_REG1=cmd;uint32_t timeout=2000000;int ok=waitCDRomIRQWithTimeout(&timeout);ackCDRomCause();readResponse(response);return ok;} static void cddaWaitPauseComplete() { initializeTime();uint32_t elapsed=0;while(elapsed< 5000000u) { uint32_t budget=200000u;int ok=waitCDRomIRQWithTimeout(&budget);elapsed=budget;if(!ok) continue;uint8_t cause=ackCDRomCause();uint8_t response[16];readResponse(response);if(cause==2) return;} } static int cddaAudioSetup(const uint8_t atv[4], int demute) { if(!resetCDRom()) return 0;DPCR|=0x000b0000;SPU_CTRL=0;for(volatile int i=0;i< 20000;i++);SPU_VOL_MAIN_LEFT=0;SPU_VOL_MAIN_RIGHT=0;SPU_KEY_OFF_LOW=0xffff;SPU_KEY_OFF_HIGH=0xffff;SPU_RAM_DTC=4;SPU_CTRL=0x8001;for(volatile int i=0;i< 20000;i++);for(int i=0;i< 0x400;i++) s_cddaCapture[i]=CDDA_MARKER;if(!cddaSpuDma(0x000, s_cddaCapture, 0x800, 0)) return 0;if(!cddaSimpleCmd(demute ? CDL_DEMUTE :CDL_MUTE)) return 0;CDROM_REG0=2;CDROM_REG2=atv[0];CDROM_REG3=atv[1];CDROM_REG0=3;CDROM_REG1=atv[2];CDROM_REG2=atv[3];CDROM_REG0=3;CDROM_REG3=0x20;CDROM_REG0=0;SPU_VOL_CD_LEFT=0x7fff;SPU_VOL_CD_RIGHT=0x7fff;SPU_CTRL=SPU_CTRL|0x8001;return 1;} static int cddaBufferPeak(unsigned *signChanges) { int peak=0;unsigned changes=0;int prev=0;for(int i=0;i< 0x200;i++) { int v=(int16_t) s_cddaCapture[i];int a=v< 0 ? -v :v;if(a > peak) peak=a;int sign=v >=0 ? 1 :-1;if(i &&sign !=prev) changes++;prev=sign;} *signChanges=changes;return peak;} static int cddaCapturePeak(unsigned *signChanges) { int peak=0;for(unsigned attempt=0;attempt< 8;attempt++) { if(attempt) { initializeTime();while(updateTime()< 250000u);} if(!cddaSpuDma(0x000, s_cddaCapture, 0x800, 1)) return -1;peak=cddaBufferPeak(signChanges);if(peak) { if(attempt) ramsyscall_printf("capture was empty %u time(s) before audio\n", attempt);break;} } return peak;} static int cddaPeak(const uint8_t atv[4], int demute, unsigned *signChanges) { if(!cddaAudioSetup(atv, demute)) return -1;if(!setMode(0)) return -1;CDROM_REG0=0;CDROM_REG2=0x02;if(!cddaSimpleCmd(CDL_PLAY)) return -1;initializeTime();while(updateTime()< 1500000u);int peak=cddaCapturePeak(signChanges);CDROM_REG0=0;CDROM_REG1=CDL_PAUSE;cddaWaitPauseComplete();CDROM_REG0=0;CDROM_REG2=0x00;CDROM_REG2=0x02;CDROM_REG2=0x16;if(cddaSimpleCmd(CDL_SETLOC) &&cddaSimpleCmd(CDL_SEEKL)) cddaWaitPauseComplete();return peak;}[0x400])
Definition cdda.c:37
#define EXPECT_LINE_ZERO_PIXEL_20_20
Definition raster-expected-phase2.h:77
#define EXPECT_LINE_H_PIXEL_5_11
Definition raster-expected-phase2.h:53
#define EXPECT_LINE_D45_PIXEL_7_7
Definition raster-expected-phase2.h:65
#define EXPECT_LINE_H_PIXEL_4_10
Definition raster-expected-phase2.h:48
#define EXPECT_LINE_ZERO_PIXEL_21_20
Definition raster-expected-phase2.h:78
#define EXPECT_LINE_V_PIXEL_10_5
Definition raster-expected-phase2.h:57
#define EXPECT_LINE_H_PIXEL_11_10
Definition raster-expected-phase2.h:52
#define EXPECT_LINE_SHALLOW_PIXEL_2_0
Definition raster-expected-phase2.h:88
#define EXPECT_LINE_V_PIXEL_10_4
Definition raster-expected-phase2.h:56
#define EXPECT_LINE_SHALLOW_PIXEL_5_2
Definition raster-expected-phase2.h:86
#define EXPECT_LINE_V_PIXEL_10_11
Definition raster-expected-phase2.h:60
#define EXPECT_LINE_V_PIXEL_10_10
Definition raster-expected-phase2.h:59
#define EXPECT_LINE_DN45_PIXEL_10_5
Definition raster-expected-phase2.h:73
#define EXPECT_LINE_H_PIXEL_7_10
Definition raster-expected-phase2.h:50
#define EXPECT_LINE_D45_PIXEL_6_5
Definition raster-expected-phase2.h:68
#define EXPECT_LINE_H_PIXEL_10_10
Definition raster-expected-phase2.h:51
#define EXPECT_LINE_SHALLOW_PIXEL_0_0
Definition raster-expected-phase2.h:85
#define EXPECT_LINE_D45_PIXEL_5_5
Definition raster-expected-phase2.h:64
#define EXPECT_LINE_H_PIXEL_5_10
Definition raster-expected-phase2.h:49
#define EXPECT_LINE_D45_PIXEL_5_6
Definition raster-expected-phase2.h:67
#define EXPECT_LINE_DN45_PIXEL_5_10
Definition raster-expected-phase2.h:71
#define EXPECT_LINE_SHALLOW_PIXEL_10_3
Definition raster-expected-phase2.h:87
#define EXPECT_LINE_V_PIXEL_10_7
Definition raster-expected-phase2.h:58
#define EXPECT_LINE_DN45_PIXEL_7_8
Definition raster-expected-phase2.h:72
#define EXPECT_LINE_D45_PIXEL_10_10
Definition raster-expected-phase2.h:66
#define RASTER_CMD_BLUE
Definition raster-helpers.h:128
#define RASTER_CMD_RED
Definition raster-helpers.h:124
#define RASTER_CMD_WHITE
Definition raster-helpers.h:130
#define RASTER_CMD_GREEN
Definition raster-helpers.h:126
#define ASSERT_PIXEL_EQ(expected, x_, y_)
Definition raster-helpers.h:473