9#ifndef SPU_ADPCM_EDGE_GOLDENS_AVAILABLE
10#define SPU_ADPCM_EDGE_GOLDENS_AVAILABLE 0
13#ifndef SPU_ADPCM_EDGE_EXPECTED_REPEAT_LOOP_START
14#define SPU_ADPCM_EDGE_EXPECTED_REPEAT_LOOP_START 0x212u
16#ifndef SPU_ADPCM_EDGE_EXPECTED_REPEAT_END_MUTE
17#define SPU_ADPCM_EDGE_EXPECTED_REPEAT_END_MUTE 0x210u
19#ifndef SPU_ADPCM_EDGE_EXPECTED_ENDX_END_MUTE
20#define SPU_ADPCM_EDGE_EXPECTED_ENDX_END_MUTE 0x1u
22#ifndef SPU_ADPCM_EDGE_EXPECTED_ENVX_END_MUTE
23#define SPU_ADPCM_EDGE_EXPECTED_ENVX_END_MUTE 0x0u
25#ifndef SPU_ADPCM_EDGE_EXPECTED_ENDX_END_REPEAT
26#define SPU_ADPCM_EDGE_EXPECTED_ENDX_END_REPEAT 0x1u
28#ifndef SPU_ADPCM_EDGE_EXPECTED_ENVX_END_REPEAT
29#define SPU_ADPCM_EDGE_EXPECTED_ENVX_END_REPEAT 0x3fffu
32#define SPU_ENDX_LOW HW_U16(0x1f801d9c)
34#if SPU_ADPCM_EDGE_GOLDENS_AVAILABLE && !defined(SPU_DUMP)
35#define SPU_ADPCM_EDGE_INCBIN(NAME) \
37 ".pushsection .rodata\n" \
38 ".global " #NAME "\n" \
41 ".incbin \"" #NAME ".test.pcm\"\n" \
45SPU_ADPCM_EDGE_INCBIN(adpcm_edge_predictor_0);
46SPU_ADPCM_EDGE_INCBIN(adpcm_edge_predictor_1);
47SPU_ADPCM_EDGE_INCBIN(adpcm_edge_predictor_2);
48SPU_ADPCM_EDGE_INCBIN(adpcm_edge_predictor_3);
49SPU_ADPCM_EDGE_INCBIN(adpcm_edge_predictor_4);
50SPU_ADPCM_EDGE_INCBIN(adpcm_edge_shift_00_03);
51SPU_ADPCM_EDGE_INCBIN(adpcm_edge_shift_04_07);
52SPU_ADPCM_EDGE_INCBIN(adpcm_edge_shift_08_11);
53SPU_ADPCM_EDGE_INCBIN(adpcm_edge_shift_12_15);
54SPU_ADPCM_EDGE_INCBIN(adpcm_edge_state_carry);
55SPU_ADPCM_EDGE_INCBIN(adpcm_edge_saturation_positive);
56SPU_ADPCM_EDGE_INCBIN(adpcm_edge_saturation_negative);
57SPU_ADPCM_EDGE_INCBIN(adpcm_edge_flag_code2_ignored);
58SPU_ADPCM_EDGE_INCBIN(adpcm_edge_flag_loop_start_latch);
59SPU_ADPCM_EDGE_INCBIN(adpcm_edge_flag_end_mute);
60SPU_ADPCM_EDGE_INCBIN(adpcm_edge_flag_end_repeat);
61SPU_ADPCM_EDGE_INCBIN(adpcm_edge_invalid_predictor_5_7);
64#undef SPU_ADPCM_EDGE_INCBIN
68static const uint8_t kEdgeZero[14] = {
69 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
70 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
72static const uint8_t kEdgePositive[14] = {
73 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,
74 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,
76static const uint8_t kEdgeNegative[14] = {
77 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
78 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
80static const uint8_t kEdgeAlternating[14] = {
81 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
82 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
84static const uint8_t kEdgeRamp[14] = {
85 0x10, 0x32, 0x54, 0x76, 0x56, 0x34, 0x12,
86 0xe0, 0xcd, 0xab, 0x89, 0xa9, 0xcb, 0xed,
88static const uint8_t kEdgeMixed[14] = {
89 0x17, 0xde, 0x9a, 0xbc, 0x45, 0x23, 0x01,
90 0xfe, 0xdc, 0xba, 0x98, 0x89, 0x67, 0x45,
94 uint8_t
flags,
const uint8_t *payload) {
95 uint8_t *p =
sample + block * 16;
98 for (
int i = 0;
i < 14;
i++) p[2 +
i] = payload[
i];
101static uint32_t spu_adpcm_edge_hash_capture(
void) {
103 for (
int i = 0;
i < 512;
i++) {
104 h ^= (uint16_t)s_capture[
i];
110static void spu_adpcm_edge_observe(
const char *name) {
111 int16_t min = (int16_t)s_capture[0];
112 int16_t max = (int16_t)s_capture[0];
113 for (
int i = 1;
i < 512;
i++) {
114 int16_t v = (int16_t)s_capture[
i];
115 if (v < min) min = v;
116 if (v > max) max = v;
118 ramsyscall_printf(
"OBS spu_adpcm_edge golden %s.test.pcm hash=0x%08x first=0x%04x mid=0x%04x last=0x%04x min=0x%04x max=0x%04x\n",
119 name, spu_adpcm_edge_hash_capture(), s_capture[0],
120 s_capture[256], s_capture[511], (uint16_t)min,
124static void spu_adpcm_edge_expect_u32(
const char *name,
uint32_t expected,
126 if (expected == 0xffffffffu) {
133static void spu_adpcm_edge_run_capture_keep_on(
const uint8_t *sample64,
136 for (
int i = 0;
i < 64;
i++) s_upload[
i] = sample64[
i];
137 for (
int i = 64;
i < 128;
i++) s_upload[
i] = 0xaa;
147 spu_wait_status_bit11_flip();
149 spu_wait_status_bit11_flip();
153static void spu_adpcm_edge_stop(
void) {
162#elif SPU_ADPCM_EDGE_GOLDENS_AVAILABLE
163#define SPU_ADPCM_EDGE_ASSERT_GOLDEN(name) \
165 extern const uint8_t name[]; \
166 cester_assert_int_eq(0, spu_compare_golden(#name, s_capture, name)); \
169#define SPU_ADPCM_EDGE_ASSERT_GOLDEN(name) spu_adpcm_edge_observe(#name)
172#define SPU_ADPCM_EDGE_TEST_PREDICTOR(N) \
173CESTER_TEST(adpcm_edge_predictor_##N, spu_tests, \
174 uint8_t sample[64]; \
175 spu_adpcm_edge_block(sample, 0, ((N) << 4) | 4, 0x04, kEdgeMixed); \
176 spu_adpcm_edge_block(sample, 1, ((N) << 4) | 4, 0x00, kEdgeRamp); \
177 spu_adpcm_edge_block(sample, 2, ((N) << 4) | 4, 0x00, kEdgeZero); \
178 spu_adpcm_edge_block(sample, 3, ((N) << 4) | 4, 0x03, kEdgeAlternating); \
179 run_voice1_with_sample(sample, 0x1000); \
180 SPU_ADPCM_EDGE_ASSERT_GOLDEN(adpcm_edge_predictor_##N); \
241 for (
int i = 0;
i < 4;
i++)
249 for (
int i = 0;
i < 4;
i++)
271 spu_adpcm_edge_run_capture_keep_on(
sample, 0x1000);
273 spu_adpcm_edge_expect_u32("repeat_loop_start",
275 spu_adpcm_edge_stop();
284 spu_adpcm_edge_run_capture_keep_on(
sample, 0x1000);
287 spu_adpcm_edge_expect_u32("repeat_end_mute",
289 spu_adpcm_edge_expect_u32("endx_end_mute",
291 spu_adpcm_edge_expect_u32("envx_end_mute",
293 spu_adpcm_edge_stop();
302 spu_adpcm_edge_run_capture_keep_on(
sample, 0x1000);
305 spu_adpcm_edge_expect_u32("endx_end_repeat",
307 spu_adpcm_edge_expect_u32("envx_end_repeat",
309 spu_adpcm_edge_stop();
CESTER_TEST(cdlGetLocL, test_instances, int resetDone=resetCDRom();if(!resetDone) { cester_assert_true(resetDone);return;} initializeTime();CDROM_REG0=0;CDROM_REG1=CDL_GETLOCL;uint32_t ackTime=waitCDRomIRQ();uint8_t cause1=ackCDRomCause();uint8_t ctrl1=CDROM_REG0 &~3;uint8_t response[16];uint8_t responseSize=readResponse(response);uint8_t ctrl2=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause1b=CDROM_REG3_UC;cester_assert_uint_eq(3, cause1);cester_assert_uint_eq(0xe0, cause1b);cester_assert_uint_eq(0x38, ctrl1);cester_assert_uint_eq(0x18, ctrl2);cester_assert_uint_eq(8, responseSize);cester_assert_uint_ge(ackTime, 500);cester_assert_uint_lt(ackTime, 7000);ramsyscall_printf("Basic getlocL, ack in %ius\n", ackTime);) CESTER_TEST(cdlGetLocLafterSeekP
cester_assert_uint_eq(5, cause1)
for(unsigned i=0;i< 17;i++)
Definition cdlid.c:205
#define SPU_VOICES
Definition spu.h:42
#define SPU_VOL_MAIN_LEFT
Definition spu.h:84
#define SPU_KEY_OFF_LOW
Definition spu.h:90
#define SPU_KEY_OFF_HIGH
Definition spu.h:91
#define SPU_CTRL
Definition spu.h:104
#define SPU_VOL_MAIN_RIGHT
Definition spu.h:85
#define CESTER_MAYBE_TEST
Definition cop0.c:34
ramsyscall_printf("=== e01_kseg1_reads_no_fill ===\n")
int i
Definition gte-regio.c:297
header
Definition mkimage.py:60
uint8_t sample[64]
Definition spu-adpcm-edge.c:190
#define SPU_ADPCM_EDGE_EXPECTED_ENDX_END_REPEAT
Definition spu-adpcm-edge.c:26
#define SPU_ADPCM_EDGE_EXPECTED_REPEAT_LOOP_START
Definition spu-adpcm-edge.c:14
#define SPU_ADPCM_EDGE_ASSERT_GOLDEN(name)
spu_tests
Definition spu-adpcm-edge.c:189
#define SPU_ENDX_LOW
Definition spu-adpcm-edge.c:32
#define SPU_ADPCM_EDGE_EXPECTED_ENVX_END_REPEAT
Definition spu-adpcm-edge.c:29
#define SPU_ADPCM_EDGE_EXPECTED_REPEAT_END_MUTE
Definition spu-adpcm-edge.c:17
spu_adpcm_edge_block(sample, 0, 0x00, 0x04, kEdgeAlternating)
#define SPU_ADPCM_EDGE_TEST_PREDICTOR(N)
#define SPU_ADPCM_EDGE_EXPECTED_ENDX_END_MUTE
Definition spu-adpcm-edge.c:20
run_voice1_with_sample(sample, 0x1000)
CESTER_BODY(static const uint8_t kEdgeZero[14]={ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, };static const uint8_t kEdgePositive[14]={ 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, };static const uint8_t kEdgeNegative[14]={ 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, };static const uint8_t kEdgeAlternating[14]={ 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, };static const uint8_t kEdgeRamp[14]={ 0x10, 0x32, 0x54, 0x76, 0x56, 0x34, 0x12, 0xe0, 0xcd, 0xab, 0x89, 0xa9, 0xcb, 0xed, };static const uint8_t kEdgeMixed[14]={ 0x17, 0xde, 0x9a, 0xbc, 0x45, 0x23, 0x01, 0xfe, 0xdc, 0xba, 0x98, 0x89, 0x67, 0x45, };static void spu_adpcm_edge_block(uint8_t *sample, int block, uint8_t header, uint8_t flags, const uint8_t *payload) { uint8_t *p=sample+block *16;p[0]=header;p[1]=flags;for(int i=0;i< 14;i++) p[2+i]=payload[i];} static uint32_t spu_adpcm_edge_hash_capture(void) { uint32_t h=2166136261u;for(int i=0;i< 512;i++) { h ^=(uint16_t) s_capture[i];h *=16777619u;} return h;} static void spu_adpcm_edge_observe(const char *name) { int16_t min=(int16_t) s_capture[0];int16_t max=(int16_t) s_capture[0];for(int i=1;i< 512;i++) { int16_t v=(int16_t) s_capture[i];if(v< min) min=v;if(v > max) max=v;} ramsyscall_printf("OBS spu_adpcm_edge golden %s.test.pcm hash=0x%08x first=0x%04x mid=0x%04x last=0x%04x min=0x%04x max=0x%04x\n", name, spu_adpcm_edge_hash_capture(), s_capture[0], s_capture[256], s_capture[511],(uint16_t) min,(uint16_t) max);} static void spu_adpcm_edge_expect_u32(const char *name, uint32_t expected, uint32_t got) { if(expected==0xffffffffu) { ramsyscall_printf("OBS spu_adpcm_edge expected %s=0x%08x\n", name, got);} else { cester_assert_uint_eq(expected, got);} } static void spu_adpcm_edge_run_capture_keep_on(const uint8_t *sample64, uint16_t pitch) { spu_reset_quiet();for(int i=0;i< 64;i++) s_upload[i]=sample64[i];for(int i=64;i< 128;i++) s_upload[i]=0xaa;spu_write_sync(SPU_UPLOAD_ADDR, s_upload, 128);SPU_CTRL=0x8000|0x4000;SPU_VOL_MAIN_LEFT=0x3fff;SPU_VOL_MAIN_RIGHT=0x3fff;SPU_KEY_OFF_LOW=0xffff;SPU_KEY_OFF_HIGH=0xffff;spu_busy_wait(800000);spu_wait_status_bit11_flip();spu_voice1_keyon(SPU_UPLOAD_ADDR, pitch);spu_wait_status_bit11_flip();spu_read_sync(0x0800, s_capture, 1024);} static void spu_adpcm_edge_stop(void) { SPU_KEY_OFF_LOW=0xffff;SPU_KEY_OFF_HIGH=0xffff;muteSpu();}) CESTER_TEST(adpcm_edge_shift_00_03
#define SPU_ADPCM_EDGE_EXPECTED_ENVX_END_MUTE
Definition spu-adpcm-edge.c:23
#define SPU_UPLOAD_ADDR
Definition spu-capamp.c:31
spu_write_sync(0x1000, s_upload, 128)
spu_read_sync(0x1000, s_readback, 0x80)
static uint16_t uint16_t flags
Definition syscalls.h:334
void uint32_t(classId, spec)