42#define MASK_SUITE_SENTINEL 0x5555u
46static void fillSuiteRegion(int16_t x, int16_t y, int16_t w, int16_t h) {
52static void drawRectSet(
void) {
54 fillSuiteRegion(0, 0, 16, 8);
58 rasterFlushPrimitive();
62static void drawRectSetThenCheck(
void) {
64 fillSuiteRegion(0, 0, 16, 8);
68 rasterFlushPrimitive();
74 rasterFlushPrimitive();
80static void drawLineSet(
void) {
82 fillSuiteRegion(0, 0, 16, 4);
86 rasterFlushPrimitive();
90static void drawLineSetThenCheck(
void) {
92 fillSuiteRegion(0, 0, 16, 4);
95 rasterFlushPrimitive();
100 rasterFlushPrimitive();
114static inline void rasterFlatTexRect(
uint32_t cmdColor, int16_t x, int16_t y,
115 int16_t w, int16_t h, uint8_t u0,
116 uint8_t v0, uint16_t clut_field) {
118 GPU_DATA = 0x64000000u | (cmdColor & 0x00ffffffu);
125static void drawTexRect4Set(
void) {
127 fillSuiteRegion(0, 0, 16, 8);
129 setTextureWindow(0, 0, 0, 0);
133 rasterFlushPrimitive();
139static void drawTexTri4Set(
void) {
141 fillSuiteRegion(0, 0, 16, 8);
143 setTextureWindow(0, 0, 0, 0);
151 rasterFlushPrimitive();
157static void drawTexTri8Set(
void) {
159 fillSuiteRegion(0, 0, 16, 8);
161 setTextureWindow(0, 0, 0, 0);
168 rasterFlushPrimitive();
174static void drawTexTri15Set(
void) {
176 fillSuiteRegion(0, 0, 16, 8);
178 setTextureWindow(0, 0, 0, 0);
185 rasterFlushPrimitive();
195CESTER_TEST(rect_mask_set_origin_has_bit15, gpu_raster_phase5,
201CESTER_TEST(rect_mask_set_interior_has_bit15, gpu_raster_phase5,
206CESTER_TEST(rect_mask_set_right_edge_excluded, gpu_raster_phase5,
211CESTER_TEST(rect_mask_check_preserves_red_in_overlap, gpu_raster_phase5,
212 drawRectSetThenCheck();
218CESTER_TEST(rect_mask_check_fills_green_in_non_overlap, gpu_raster_phase5,
219 drawRectSetThenCheck();
225CESTER_TEST(rect_mask_check_red_untouched_left, gpu_raster_phase5,
226 drawRectSetThenCheck();
235CESTER_TEST(line_mask_set_start_has_bit15, gpu_raster_phase5,
240CESTER_TEST(line_mask_set_mid_has_bit15, gpu_raster_phase5,
245CESTER_TEST(line_mask_set_end_inclusive, gpu_raster_phase5,
251CESTER_TEST(line_mask_check_preserves_overlap, gpu_raster_phase5,
252 drawLineSetThenCheck();
256CESTER_TEST(line_mask_check_fills_new_pixel, gpu_raster_phase5,
257 drawLineSetThenCheck();
265CESTER_TEST(texrect4_mask_set_origin_has_bit15, gpu_raster_phase5,
270 uint16_t expected = (uint16_t)(expectedClut4Color(1) | 0x8000);
274CESTER_TEST(texrect4_mask_set_interior_has_bit15, gpu_raster_phase5,
277 uint16_t expected = (uint16_t)(expectedClut4Color(3) | 0x8000);
281CESTER_TEST(texrect4_mask_set_right_edge_excluded, gpu_raster_phase5,
290CESTER_TEST(textri4_mask_set_origin, gpu_raster_phase5,
293 uint16_t expected = (uint16_t)(expectedClut4Color(1) | 0x8000);
297CESTER_TEST(textri4_mask_set_interior, gpu_raster_phase5,
299 uint16_t expected = (uint16_t)(expectedClut4Color(2) | 0x8000);
303CESTER_TEST(textri4_mask_set_right_edge_excluded, gpu_raster_phase5,
308CESTER_TEST(textri8_mask_set_origin, gpu_raster_phase5,
310 uint16_t expected = (uint16_t)(expectedClut8Color(1) | 0x8000);
314CESTER_TEST(textri8_mask_set_interior, gpu_raster_phase5,
316 uint16_t expected = (uint16_t)(expectedClut8Color(2) | 0x8000);
320CESTER_TEST(textri15_mask_set_origin, gpu_raster_phase5,
323 uint16_t expected = (uint16_t)(expectedTex15Color(1, 1) | 0x8000);
327CESTER_TEST(textri15_mask_set_interior, gpu_raster_phase5,
329 uint16_t expected = (uint16_t)(expectedTex15Color(2, 2) | 0x8000);
333CESTER_TEST(textri15_mask_set_right_edge_excluded, gpu_raster_phase5,
CESTER_BODY(static int s_got40;static int s_got80;static uint32_t s_cause;static uint32_t s_epc;static uint32_t s_from;static uint32_t *s_resume;static uint32_t *s_regs;static uint32_t(*s_customhandler)()=NULL;static uint32_t s_oldIMASK;static uint32_t s_oldDPCR;static uint32_t s_oldDICR;uint32_t handler(uint32_t *regs, uint32_t from) { if(from==0x40) s_got40=1;if(from==0x80) s_got80=1;uint32_t cause;uint32_t epc;s_from=from;asm("mfc0 %0, $13\nnop\nmfc0 %1, $14\nnop" :"=r"(cause), "=r"(epc));s_cause=cause;s_epc=epc;if(s_customhandler) { return s_customhandler();} else { return s_resume ?((uint32_t) s_resume) :(epc+4);} } void installExceptionHandlers(uint32_t(*handler)(uint32_t *regs, uint32_t from));void uninstallExceptionHandlers();uint32_t branchbranch1();uint32_t branchbranch2();uint32_t jumpjump1();uint32_t jumpjump2();uint32_t cpu_LWR_LWL_half(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_nodelay(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_delayed(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_load_different(uint32_t buff[], uint32_t initial);uint32_t cpu_LW_LWR(uint32_t buff[], uint32_t initial);uint32_t cpu_delayed_load(uint32_t buff[], uint32_t override);uint32_t cpu_delayed_load_cancelled(uint32_t buff[], uint32_t override);uint64_t cpu_delayed_load_load(uint32_t buff[], uint32_t override);uint32_t linkandload();uint32_t lwandlink();uint32_t nolink();static int s_interruptsWereEnabled;) CESTER_BEFORE_EACH(cpu_tests
CESTER_TEST(cpu_cop0_basic_write_bp, cpu_tests, uint32_t expectedEPC;uint32_t t;volatile uint32_t *ptr=(volatile uint32_t *) 0x58; *ptr=1;__asm__ volatile("" " lui %0, 0b1100101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0xfffffff0\n" " mtc0 %0, $9\n" :"=r"(t));cester_assert_uint_eq(1, *ptr);__asm__ volatile("la %0, 1f\n1:\nsw $0, 0x58($0)" :"=r"(expectedEPC));__asm__ volatile("mtc0 $0, $7\n");cester_assert_uint_eq(0, *ptr);cester_assert_uint_eq(1, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0x40, s_from);cester_assert_uint_eq(expectedEPC, s_epc);) CESTER_TEST(cpu_cop0_kseg_write_bp
#define MASK_SUITE_SENTINEL
Definition cross-primitive-mask.c:42
#define GPU_DATA
Definition hwregs.h:52
#define RASTER_VRAM_GREEN
Definition raster-helpers.h:126
#define RASTER_CMD_RED
Definition raster-helpers.h:123
#define RASTER_CMD_GREEN
Definition raster-helpers.h:125
#define ASSERT_PIXEL_EQ(expected, x_, y_)
Definition raster-helpers.h:472
void uint32_t(classId, spec)
#define CLUT8_FIELD
Definition texture-fixtures.h:84
#define TEX15_TY
Definition texture-fixtures.h:66
#define TEX8_TY
Definition texture-fixtures.h:61
#define CLUT4_FIELD
Definition texture-fixtures.h:83
#define TEX15_TPAGE
Definition texture-fixtures.h:104
#define TEX8_TPAGE
Definition texture-fixtures.h:103
#define CLUT15_FIELD
Definition texture-fixtures.h:85
#define TEX15_TX
Definition texture-fixtures.h:65
#define TEX8_TX
Definition texture-fixtures.h:60
#define TEX_MOD_NEUTRAL
Definition texture-fixtures.h:328
#define TEX4_TY
Definition texture-fixtures.h:56
#define TEX4_TX
Definition texture-fixtures.h:55
#define TEX4_TPAGE
Definition texture-fixtures.h:102