gpu.hh

Go to the documentation of this file.

/*
 
MIT License
 
Copyright (c) 2022 PCSX-Redux authors
 
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
 
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
 
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
 
*/
 
#pragma once
 
#include <EASTL/array.h>
#include <EASTL/atomic.h>
#include <EASTL/fixed_list.h>
#include <EASTL/functional.h>
#include <EASTL/utility.h>
#include <stdint.h>
 
#include <coroutine>
 
#include "psyqo/fragment-concept.hh"
#include "psyqo/hardware/gpu.hh"
#include "psyqo/kernel.hh"
#include "psyqo/ordering-table.hh"
#include "psyqo/primitive-concept.hh"
#include "psyqo/primitives/common.hh"
#include "psyqo/primitives/control.hh"
#include "psyqo/primitives/misc.hh"
#include "psyqo/shared.hh"
 
namespace psyqo {
 
namespace DMA {
 
enum DmaCallback {
    FROM_ISR,
    FROM_MAIN_LOOP,
};
 
}
 
namespace timer_literals {
 
consteval uint32_t operator""_ns(unsigned long long int value) { return value / 1'000; }
consteval uint32_t operator""_us(unsigned long long int value) { return value; }
consteval uint32_t operator""_ms(unsigned long long int value) { return value * 1'000; }
consteval uint32_t operator""_s(unsigned long long int value) { return value * 1'000'000; }
consteval uint32_t operator""_ns(long double value) { return value / 1'000; }
consteval uint32_t operator""_us(long double value) { return value; }
consteval uint32_t operator""_ms(long double value) { return value * 1'000; }
consteval uint32_t operator""_s(long double value) { return value * 1'000'000; }
 
}  // namespace timer_literals
 
class GPU {
    struct TimerAwaiter {
        TimerAwaiter(GPU &gpu, uint32_t deadline) : m_gpu(gpu), m_deadline(deadline) {}
        ~TimerAwaiter() {}
        constexpr bool await_ready() const { return false; }
        void await_suspend(std::coroutine_handle<> handle) {
            m_gpu.armTimer(m_deadline, [handle](uint32_t) { handle.resume(); });
        }
        void await_resume() {}
        GPU &m_gpu;
        uintptr_t m_deadline;
    };
 
  public:
    struct Configuration;
    enum class Resolution { W256, W320, W368, W512, W640 };
    enum class VideoMode { AUTO, NTSC, PAL };
    enum class ColorMode { C15BITS, C24BITS };
    enum class Interlace { PROGRESSIVE, INTERLACED };
    enum class MiscSetting { CLEAR_VRAM, KEEP_VRAM };
    void initialize(const Configuration &config);
    void reinitialize(const Configuration &config);
 
    static constexpr uint32_t US_PER_HBLANK = 64;
    static constexpr unsigned c_chainThreshold = 56;
 
    unsigned getRefreshRate() const { return m_refreshRate; }
 
    uint32_t getFrameCount() const { return m_previousFrameCount; }
 
    unsigned getParity() const { return m_parity; }
 
    void clear(Color bg = {{0, 0, 0}});
 
    void getClear(Prim::FastFill &ff, Color bg = {{0, 0, 0}}) const;
 
    void getNextClear(Prim::FastFill &ff, Color bg = {{0, 0, 0}}) const;
 
    void uploadToVRAM(const uint16_t *data, Rect region);
 
    void uploadToVRAM(const uint16_t *data, Rect region, eastl::function<void()> &&callback,
                      DMA::DmaCallback dmaCallback = DMA::FROM_MAIN_LOOP);
 
    template <Fragment Frag>
    void sendFragment(const Frag &fragment) {
        sendFragment(reinterpret_cast<const uint32_t *>(&fragment.head + 1), fragment.getActualFragmentSize());
    }
 
    template <Fragment Frag>
    void sendFragment(const Frag &fragment, eastl::function<void()> &&callback,
                      DMA::DmaCallback dmaCallback = DMA::FROM_MAIN_LOOP) {
        sendFragment(reinterpret_cast<const uint32_t *>(&fragment.head + 1), fragment.getActualFragmentSize(),
                     eastl::move(callback), dmaCallback);
    }
 
    void disableScissor();
 
    void enableScissor();
 
    void getScissor(Prim::Scissor &scissor);
 
    void getNextScissor(Prim::Scissor &scissor);
 
    void waitReady();
 
    void waitFifo();
 
    static void sendRaw(uint32_t data) { Hardware::GPU::Data = data; }
 
    template <Primitive Prim>
    void sendPrimitive(const Prim &primitive) {
        waitReady();
        const uint32_t *ptr = reinterpret_cast<const uint32_t *>(&primitive);
        constexpr size_t size = sizeof(Prim) / sizeof(uint32_t);
        for (int i = 0; i < size; i++) {
            if constexpr (sizeof(Prim) > c_chainThreshold) waitFifo();
            sendRaw(*ptr++);
        }
    }
 
    template <Fragment Frag>
    void chain(Frag &fragment) {
        chain(&fragment.head, &fragment.head, fragment.getActualFragmentSize());
    }
 
    template <Fragment Frag1, Fragment Frag2>
    void chain(Frag1 *first, Frag2 *last) {
        auto count = last->getActualFragmentSize();
        Kernel::assert(count <= (c_chainThreshold / 4), "Last element of the chain is too big");
        chain(&first->head, &last->head, last->getActualFragmentSize());
    }
 
    template <size_t N, Safe safety = Safe::Yes>
    void chain(OrderingTable<N, safety> &table) {
        chain(&table.m_table[N].head, &table.m_table[0].head, 0);
        scheduleOTC(&table.m_table[N].head, N + 1);
    }
 
    void sendChain();
 
    void sendChain(eastl::function<void()> &&callback, DMA::DmaCallback dmaCallback = DMA::FROM_MAIN_LOOP);
 
    bool isChainIdle() const;
 
    bool isChainTransferring() const;
 
    bool isChainTransferred() const;
 
    void waitChainIdle() {
        while (isChainTransferring()) pumpCallbacks();
    }
 
    uint32_t now() const { return m_currentTime; }
 
    uintptr_t armTimer(uint32_t deadline, eastl::function<void(uint32_t)> &&callback);
 
    TimerAwaiter delay(uint32_t microseconds) { return {*this, now() + microseconds}; }
 
    unsigned armPeriodicTimer(uint32_t period, eastl::function<void(uint32_t)> &&callback);
 
    void changeTimerPeriod(uintptr_t id, uint32_t period, bool reset = false);
 
    void pauseTimer(uintptr_t id);
 
    void resumeTimer(uintptr_t id);
 
    void cancelTimer(uintptr_t id);
 
    void pumpCallbacks();
 
  private:
    GPU();
    GPU(const GPU &) = delete;
    GPU(GPU &&) = delete;
    GPU &operator=(const GPU &) = delete;
    GPU &operator=(GPU &&) = delete;
    void sendFragment(const uint32_t *data, size_t count);
    void sendFragment(const uint32_t *data, size_t count, eastl::function<void()> &&callback,
                      DMA::DmaCallback dmaCallback);
    void scheduleNormalDMA(uintptr_t data, size_t count);
    void scheduleChainedDMA(uintptr_t head);
    void chain(uintptr_t *first, uintptr_t *last, size_t count);
    void scheduleOTC(uintptr_t *start, uint32_t count);
    void checkOTCAndTriggerCallback();
    void prepareForTakeover();
 
    eastl::function<void(void)> m_dmaCallback = nullptr;
    unsigned m_refreshRate = 0;
    int m_width = 0;
    int m_height = 0;
    uint32_t m_currentTime = 0;
    uint32_t m_frameCount = 0;
    uint32_t m_previousFrameCount = 0;
    unsigned m_parity = 0;
    uintptr_t *m_chainHead = nullptr;
    uintptr_t *m_chainTail = nullptr;
    size_t m_chainTailCount = 0;
    enum { CHAIN_IDLE, CHAIN_TRANSFERRING, CHAIN_TRANSFERRED } m_chainStatus = CHAIN_IDLE;
    struct Timer {
        eastl::function<void(uint32_t)> callback;
        uint32_t deadline;
        uint32_t period;
        int32_t pausedRemaining;
        bool periodic;
        bool paused = false;
    };
    eastl::fixed_list<Timer, 32> m_timers;
    struct ScheduledOTC {
        uintptr_t *start;
        uint32_t count;
    };
    eastl::fixed_list<ScheduledOTC, 32> m_OTCs[2];
    uintptr_t *m_chainNext = nullptr;
 
    uint16_t m_lastHSyncCounter = 0;
    bool m_interlaced = false;
    bool m_fromISR = false;
    bool m_flushCacheAfterDMA = false;
 
    void flip();
    friend class Application;
    friend void psyqo::Kernel::takeOverKernel();
};
 
}  // namespace psyqo
 
#include "psyqo/internal/gpu/configuration.hh"