#include "common/hardware/hwregs.h"
#include "common/syscalls/syscalls.h"
#include "exotic/cester.h"

Include dependency graph for icache.c:

Macros
#define	PCSX_TESTS 0

#define	CESTER_MAYBE_TEST CESTER_TEST

#define	CESTER_NO_SIGNAL

#define	CESTER_NO_TIME

#define	EXIT_SUCCESS 0

#define	EXIT_FAILURE 1

#define	MIPS_JR_RA 0x03e00008

#define	MIPS_NOP 0x00000000

#define	TEST_BASE ((uint32_t)s_testArea + 0x800)

#define	TEST_BASE_UNC (TEST_BASE \| 0x20000000)

#define	TEST_LINE 128 /* CACHE_LINE_INDEX(TEST_BASE), checked in fill_pattern */

#define	TEST_ALT (TEST_BASE + 0x1000)

#define	TEST_ALT_UNC (TEST_ALT \| 0x20000000)

#define	CACHE_LINE_INDEX(addr) (((uint32_t)(addr) >> 4) & 0xff)

#define	TAG_VALID(x) ((x) & 0x0f)

#define	TAG_MATCH(x) (((x) >> 4) & 1)

#define	BIU_NORMAL 0x0001e988 /* Default: RAM\|DS\|IBLKSZ_4\|IS1\|RDPRI\|NOPAD\|BGNT\|LDSCH */

#define	BIU_IBLKSZ_2WORD 0x0001e888 /* 2-word refill: clear IBLKSZ bit 8 */

Functions
	CESTER_BODY (extern void icache_read_tag_line(uint32_t addr, uint32_t out);extern void icache_read_code_line(unsigned line_index, uint32_t out);extern void icache_flush_all_tags(void);extern void icache_write_tag(uint32_t addr, uint32_t value);extern void icache_write_code_word(unsigned word_index, uint32_t value);extern uint32_t icache_read_biu(void);extern void icache_fill_with_biu(uint32_t cached_addr, uint32_t biu_value);static uint32_t s_testArea __attribute__((aligned(4096)));static int s_interruptsWereEnabled;static uint32_t s_tagbuf;static uint32_t s_codebuf;[2048][4][4])

	cester_assert_uint_eq (TEST_LINE, CACHE_LINE_INDEX(TEST_BASE))

	cester_assert_uint_eq (TEST_LINE, CACHE_LINE_INDEX(TEST_ALT))

	ramsyscall_printf ("=== Fill pattern (line %d) ===\n", TEST_LINE)

	ramsyscall_printf (" Word0 Word1 Word2 Word3\n")

	for (int b=0;b< 2;b++)

	CESTER_TEST (tag_is_physical, icache_tests, volatile uint32_t unc=(volatile uint32_t ) TEST_BASE_UNC;volatile uint32_t unc_alt=(volatile uint32_t ) TEST_ALT_UNC;unc[0]=MIPS_JR_RA;unc[1]=MIPS_NOP;unc[2]=MIPS_NOP;unc[3]=MIPS_NOP;unc_alt[0]=MIPS_JR_RA;unc_alt[1]=MIPS_NOP;unc_alt[2]=MIPS_NOP;unc_alt[3]=MIPS_NOP;ramsyscall_printf("=== Tag is physical address ===\n");icache_flush_all_tags();((void()(void)) TEST_BASE)();icache_read_tag_line(TEST_BASE, s_tagbuf);uint32_t base_match=TAG_MATCH(s_tagbuf[0]);ramsyscall_printf("BASE %08lx: valid=0x%lx match=%ld\n", TEST_BASE,(uint32_t) TAG_VALID(s_tagbuf[0]), base_match);icache_flush_all_tags();((void()(void)) TEST_ALT)();icache_read_tag_line(TEST_BASE, s_tagbuf);ramsyscall_printf("ALT %08lx: valid=0x%lx match=%ld\n", TEST_ALT,(uint32_t) TAG_VALID(s_tagbuf[0]),(uint32_t) TAG_MATCH(s_tagbuf[0]));cester_assert_uint_eq(1, base_match);cester_assert_uint_eq(0, TAG_MATCH(s_tagbuf[0]));) CESTER_TEST(valid_bits_controllable

Variables
const char *	names [] = { "IBLKSZ=0(2w)", "IBLKSZ=1(4w)" }

uint32_t	valid [2][4]

	icache_tests

uint32_t	patterns [] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x5, 0xA, 0xF }

int	n = sizeof(patterns) / sizeof(patterns[0])

Macro Definition Documentation

◆ BIU_IBLKSZ_2WORD

#define BIU_IBLKSZ_2WORD 0x0001e888 /* 2-word refill: clear IBLKSZ bit 8 */

◆ BIU_NORMAL

#define BIU_NORMAL 0x0001e988 /* Default: RAM|DS|IBLKSZ_4|IS1|RDPRI|NOPAD|BGNT|LDSCH */

◆ CACHE_LINE_INDEX

#define CACHE_LINE_INDEX ( addr ) (((uint32_t)(addr) >> 4) & 0xff)

◆ CESTER_MAYBE_TEST

#define CESTER_MAYBE_TEST CESTER_TEST

◆ CESTER_NO_SIGNAL

#define CESTER_NO_SIGNAL

◆ CESTER_NO_TIME

#define CESTER_NO_TIME

◆ EXIT_FAILURE

#define EXIT_FAILURE 1

◆ EXIT_SUCCESS

#define EXIT_SUCCESS 0

◆ MIPS_JR_RA

#define MIPS_JR_RA 0x03e00008

◆ MIPS_NOP

#define MIPS_NOP 0x00000000

◆ PCSX_TESTS

#define PCSX_TESTS 0

◆ TAG_MATCH

#define TAG_MATCH ( x ) (((x) >> 4) & 1)

◆ TAG_VALID

#define TAG_VALID ( x ) ((x) & 0x0f)

◆ TEST_ALT

#define TEST_ALT (TEST_BASE + 0x1000)

◆ TEST_ALT_UNC

#define TEST_ALT_UNC (TEST_ALT | 0x20000000)

◆ TEST_BASE

#define TEST_BASE ((uint32_t)s_testArea + 0x800)

◆ TEST_BASE_UNC

#define TEST_BASE_UNC (TEST_BASE | 0x20000000)

◆ TEST_LINE

#define TEST_LINE 128 /* CACHE_LINE_INDEX(TEST_BASE), checked in fill_pattern */

Function Documentation

◆ cester_assert_uint_eq() [1/2]

cester_assert_uint_eq	(	TEST_LINE	,
		CACHE_LINE_INDEX(TEST_ALT)
	)

◆ cester_assert_uint_eq() [2/2]

cester_assert_uint_eq	(	TEST_LINE	,
		CACHE_LINE_INDEX(TEST_BASE)
	)

◆ CESTER_BODY()

CESTER_BODY ( extern void icache_read_tag_line(uint32_t addr, uint32_t *out);extern void icache_read_code_line(unsigned line_index, uint32_t *out);extern void icache_flush_all_tags(void);extern void icache_write_tag(uint32_t addr, uint32_t value);extern void icache_write_code_word(unsigned word_index, uint32_t value);extern uint32_t icache_read_biu(void);extern void icache_fill_with_biu(uint32_t cached_addr, uint32_t biu_value);static uint32_t s_testArea __attribute__((aligned(4096)));static int s_interruptsWereEnabled;static uint32_t s_tagbuf;static uint32_t s_codebuf; [2048][4][4] )

◆ CESTER_TEST()

CESTER_TEST	(	tag_is_physical	,
		icache_tests	,
		volatile uint32_t *	unc = (volatile uint32_t )TEST_BASE_UNC; volatile uint32_t unc_alt = (volatile uint32_t )TEST_ALT_UNC; unc[0] = MIPS_JR_RA; unc[1] = MIPS_NOP; unc[2] = MIPS_NOP; unc[3] = MIPS_NOP; unc_alt[0] = MIPS_JR_RA; unc_alt[1] = MIPS_NOP; unc_alt[2] = MIPS_NOP; unc_alt[3] = MIPS_NOP; ramsyscall_printf("=== Tag is physical address ===\n"); icache_flush_all_tags(); ((void ()(void))TEST_BASE)(); icache_read_tag_line(TEST_BASE, s_tagbuf); uint32_t base_match = TAG_MATCH(s_tagbuf[0]); ramsyscall_printf("BASE %08lx: valid=0x%lx match=%ld\n", TEST_BASE, (uint32_t)TAG_VALID(s_tagbuf[0]), base_match); icache_flush_all_tags(); ((void (*)(void))TEST_ALT)(); icache_read_tag_line(TEST_BASE, s_tagbuf); ramsyscall_printf("ALT %08lx: valid=0x%lx match=%ld\n", TEST_ALT, (uint32_t)TAG_VALID(s_tagbuf[0]), (uint32_t)TAG_MATCH(s_tagbuf[0])); cester_assert_uint_eq(1, base_match); cester_assert_uint_eq(0, TAG_MATCH(s_tagbuf[0]));
	)

◆ for()

for ( )

◆ ramsyscall_printf() [1/2]

ramsyscall_printf ( " Word0 Word1 Word2 Word3\n" )

◆ ramsyscall_printf() [2/2]

ramsyscall_printf ( )

Variable Documentation

◆ icache_tests

icache_tests

◆ n

int n = sizeof(patterns) / sizeof(patterns[0])

◆ names

const char* names[] = { "IBLKSZ=0(2w)", "IBLKSZ=1(4w)" }

◆ patterns

uint32_t patterns[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x5, 0xA, 0xF }

◆ valid

uint32_t valid[2][4]

Macros

Functions

Variables