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affine-triangles.c
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1/*
2
3MIT License
4
5Copyright (c) 2026 PCSX-Redux authors
6
7Permission is hereby granted, free of charge, to any person obtaining a copy
8of this software and associated documentation files (the "Software"), to deal
9in the Software without restriction, including without limitation the rights
10to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11copies of the Software, and to permit persons to whom the Software is
12furnished to do so, subject to the following conditions:
13
14The above copyright notice and this permission notice shall be included in all
15copies or substantial portions of the Software.
16
17THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23SOFTWARE.
24
25*/
26
27// Phase-17 affine UV-mapping triangle suite. Eight triangles spanning
28// the parameter space: UV-vs-screen rotation, scale ratios, and
29// stress geometries (narrow-tall, flat-wide).
30//
31// All draws use the phase-17 TEX17 signature texture (texpage cell
32// TX=11, 32x32 15-bit direct). Texel(u, v) encodes (u, v) uniquely in
33// (red, green) channels so probe failures decode directly into the
34// (u, v) the rasterizer actually sampled.
35
37
38// ---- T1 AR_AXIS_BASE -----------------------------------------------------
39// A=(5,5)/(0,0) B=(25,5)/(20,0) C=(5,15)/(0,10)
40// Affine: UV(x, y) = (x - 5, y - 5). 1:1 ratio, axis-aligned.
41
42static void drawAR_AXIS_BASE(void) {
43 rasterReset();
44 rasterClearTestRegion(0, 0, 32, 16);
45 setTexpage(TEX17_TX, TEX17_TY, 2);
46 setTextureWindow(0, 0, 0, 0);
47 rasterTexTri(TEX_MOD_NEUTRAL,
48 5, 5, 0, 0,
49 25, 5, 20, 0,
50 5, 15, 0, 10,
52 rasterFlushPrimitive();
53}
54
55// ---- T2 AR_COMPRESS ------------------------------------------------------
56// A=(5,5)/(0,0) B=(35,5)/(6,0) C=(5,15)/(0,3)
57// 30x10 screen -> 6x3 UV. Sub-unit per-pixel UV step.
58
59static void drawAR_COMPRESS(void) {
60 rasterReset();
61 rasterClearTestRegion(0, 0, 48, 16);
62 setTexpage(TEX17_TX, TEX17_TY, 2);
63 setTextureWindow(0, 0, 0, 0);
64 rasterTexTri(TEX_MOD_NEUTRAL,
65 5, 5, 0, 0,
66 35, 5, 6, 0,
67 5, 15, 0, 3,
69 rasterFlushPrimitive();
70}
71
72// ---- T3 AR_STRETCH -------------------------------------------------------
73// A=(5,5)/(0,0) B=(15,5)/(30,0) C=(5,10)/(0,20)
74// 10x5 screen -> 30x20 UV. Per-pixel UV step ~3x and ~4x.
75
76static void drawAR_STRETCH(void) {
77 rasterReset();
78 rasterClearTestRegion(0, 0, 16, 16);
79 setTexpage(TEX17_TX, TEX17_TY, 2);
80 setTextureWindow(0, 0, 0, 0);
81 rasterTexTri(TEX_MOD_NEUTRAL,
82 5, 5, 0, 0,
83 15, 5, 30, 0,
84 5, 10, 0, 20,
86 rasterFlushPrimitive();
87}
88
89// ---- T4 AR_TWIST_90 ------------------------------------------------------
90// A=(4,4)/(0,0) B=(20,4)/(0,16) C=(4,20)/(16,0)
91// UV axes swapped. UV(x, y) = (y - 4, x - 4) inside triangle.
92// Tests cross-span UV step at maximum rate vs zero row-edge step.
93
94static void drawAR_TWIST_90(void) {
95 rasterReset();
96 rasterClearTestRegion(0, 0, 24, 24);
97 setTexpage(TEX17_TX, TEX17_TY, 2);
98 setTextureWindow(0, 0, 0, 0);
99 rasterTexTri(TEX_MOD_NEUTRAL,
100 4, 4, 0, 0,
101 20, 4, 0, 16,
102 4, 20, 16, 0,
104 rasterFlushPrimitive();
105}
106
107// ---- T5 AR_TWIST_45 ------------------------------------------------------
108// A=(4,4)/(8,0) B=(20,4)/(16,8) C=(4,20)/(0,8)
109// UV rotated 45 degrees. dU/dX = 0.5, dU/dY = -0.5, dV/dX = 0.5,
110// dV/dY = 0.5 (uniform-magnitude in both UV axes).
111
112static void drawAR_TWIST_45(void) {
113 rasterReset();
114 rasterClearTestRegion(0, 0, 24, 24);
115 setTexpage(TEX17_TX, TEX17_TY, 2);
116 setTextureWindow(0, 0, 0, 0);
117 rasterTexTri(TEX_MOD_NEUTRAL,
118 4, 4, 8, 0,
119 20, 4, 16, 8,
120 4, 20, 0, 8,
122 rasterFlushPrimitive();
123}
124
125// ---- T6 AR_NATURAL -------------------------------------------------------
126// A=(5,5)/(3,2) B=(25,9)/(20,5) C=(8,22)/(8,22)
127// Arbitrary triangle, arbitrary UV. No symmetry, no special structure.
128
129static void drawAR_NATURAL(void) {
130 rasterReset();
131 rasterClearTestRegion(0, 0, 32, 24);
132 setTexpage(TEX17_TX, TEX17_TY, 2);
133 setTextureWindow(0, 0, 0, 0);
134 rasterTexTri(TEX_MOD_NEUTRAL,
135 5, 5, 3, 2,
136 25, 9, 20, 5,
137 8, 22, 8, 22,
139 rasterFlushPrimitive();
140}
141
142// ---- T7 AR_NARROW_TALL ---------------------------------------------------
143// A=(10,4)/(0,0) B=(14,4)/(20,0) C=(12,24)/(10,30)
144// 4 wide, 20 tall. Cross-span UV step dominates row edge step.
145
146static void drawAR_NARROW_TALL(void) {
147 rasterReset();
148 rasterClearTestRegion(4, 0, 16, 28);
149 setTexpage(TEX17_TX, TEX17_TY, 2);
150 setTextureWindow(0, 0, 0, 0);
151 rasterTexTri(TEX_MOD_NEUTRAL,
152 10, 4, 0, 0,
153 14, 4, 20, 0,
154 12, 24, 10, 30,
156 rasterFlushPrimitive();
157}
158
159// ---- T8 AR_FLAT_WIDE -----------------------------------------------------
160// A=(4,8)/(0,0) B=(34,9)/(30,0) C=(4,11)/(0,4)
161// 30 wide, 3 tall. Row edge step dominates cross-span step.
162
163static void drawAR_FLAT_WIDE(void) {
164 rasterReset();
165 rasterClearTestRegion(0, 0, 48, 16);
166 setTexpage(TEX17_TX, TEX17_TY, 2);
167 setTextureWindow(0, 0, 0, 0);
168 rasterTexTri(TEX_MOD_NEUTRAL,
169 4, 8, 0, 0,
170 34, 9, 30, 0,
171 4, 11, 0, 4,
173 rasterFlushPrimitive();
174}
175
176) // CESTER_BODY
177
178// --------------------------------------------------------------------------
179// T1 AR_AXIS_BASE assertions
180// --------------------------------------------------------------------------
181
182CESTER_TEST(ar_axis_base_10_8, gpu_raster_phase17,
183 drawAR_AXIS_BASE();
185)
186
187CESTER_TEST(ar_axis_base_20_6, gpu_raster_phase17,
188 drawAR_AXIS_BASE();
190)
191
192CESTER_TEST(ar_axis_base_8_12, gpu_raster_phase17,
193 drawAR_AXIS_BASE();
195)
196
197CESTER_TEST(ar_axis_base_24_5_top_edge, gpu_raster_phase17,
198 drawAR_AXIS_BASE();
200)
201
202CESTER_TEST(ar_axis_base_25_5_right_vert_excluded, gpu_raster_phase17,
203 drawAR_AXIS_BASE();
205)
206
207// --------------------------------------------------------------------------
208// T2 AR_COMPRESS assertions
209// --------------------------------------------------------------------------
210
211CESTER_TEST(ar_compress_10_7, gpu_raster_phase17,
212 drawAR_COMPRESS();
214)
215
216CESTER_TEST(ar_compress_20_8, gpu_raster_phase17,
217 drawAR_COMPRESS();
219)
220
221CESTER_TEST(ar_compress_15_10, gpu_raster_phase17,
222 drawAR_COMPRESS();
224)
225
226CESTER_TEST(ar_compress_30_5, gpu_raster_phase17,
227 drawAR_COMPRESS();
229)
230
231// --------------------------------------------------------------------------
232// T3 AR_STRETCH assertions
233// --------------------------------------------------------------------------
234
235CESTER_TEST(ar_stretch_6_6, gpu_raster_phase17,
236 drawAR_STRETCH();
238)
239
240CESTER_TEST(ar_stretch_10_7, gpu_raster_phase17,
241 drawAR_STRETCH();
243)
244
245CESTER_TEST(ar_stretch_8_8, gpu_raster_phase17,
246 drawAR_STRETCH();
248)
249
250CESTER_TEST(ar_stretch_5_5_a_vert, gpu_raster_phase17,
251 drawAR_STRETCH();
253)
254
255// --------------------------------------------------------------------------
256// T4 AR_TWIST_90 assertions
257// --------------------------------------------------------------------------
258
259CESTER_TEST(ar_twist_90_10_10, gpu_raster_phase17,
260 drawAR_TWIST_90();
262)
263
264CESTER_TEST(ar_twist_90_6_10, gpu_raster_phase17,
265 drawAR_TWIST_90();
267)
268
269CESTER_TEST(ar_twist_90_10_6, gpu_raster_phase17,
270 drawAR_TWIST_90();
272)
273
274CESTER_TEST(ar_twist_90_4_4_a_vert, gpu_raster_phase17,
275 drawAR_TWIST_90();
277)
278
279// --------------------------------------------------------------------------
280// T5 AR_TWIST_45 assertions
281// --------------------------------------------------------------------------
282
283CESTER_TEST(ar_twist_45_12_4_ab_mid, gpu_raster_phase17,
284 drawAR_TWIST_45();
286)
287
288CESTER_TEST(ar_twist_45_4_12_ac_mid, gpu_raster_phase17,
289 drawAR_TWIST_45();
291)
292
293CESTER_TEST(ar_twist_45_8_8, gpu_raster_phase17,
294 drawAR_TWIST_45();
296)
297
298CESTER_TEST(ar_twist_45_12_12_bc_mid, gpu_raster_phase17,
299 drawAR_TWIST_45();
301)
302
303// --------------------------------------------------------------------------
304// T6 AR_NATURAL assertions
305// --------------------------------------------------------------------------
306
307CESTER_TEST(ar_natural_12_10, gpu_raster_phase17,
308 drawAR_NATURAL();
310)
311
312CESTER_TEST(ar_natural_18_15, gpu_raster_phase17,
313 drawAR_NATURAL();
315)
316
317CESTER_TEST(ar_natural_10_18, gpu_raster_phase17,
318 drawAR_NATURAL();
320)
321
322CESTER_TEST(ar_natural_5_5_a_vert, gpu_raster_phase17,
323 drawAR_NATURAL();
325)
326
327// --------------------------------------------------------------------------
328// T7 AR_NARROW_TALL assertions
329// --------------------------------------------------------------------------
330
331CESTER_TEST(ar_narrow_tall_11_8, gpu_raster_phase17,
332 drawAR_NARROW_TALL();
334)
335
336CESTER_TEST(ar_narrow_tall_12_14, gpu_raster_phase17,
337 drawAR_NARROW_TALL();
339)
340
341CESTER_TEST(ar_narrow_tall_11_20, gpu_raster_phase17,
342 drawAR_NARROW_TALL();
344)
345
346CESTER_TEST(ar_narrow_tall_13_6, gpu_raster_phase17,
347 drawAR_NARROW_TALL();
349)
350
351// --------------------------------------------------------------------------
352// T8 AR_FLAT_WIDE assertions
353// --------------------------------------------------------------------------
354
355CESTER_TEST(ar_flat_wide_8_9, gpu_raster_phase17,
356 drawAR_FLAT_WIDE();
358)
359
360CESTER_TEST(ar_flat_wide_20_9, gpu_raster_phase17,
361 drawAR_FLAT_WIDE();
363)
364
365CESTER_TEST(ar_flat_wide_30_9, gpu_raster_phase17,
366 drawAR_FLAT_WIDE();
368)
369
370CESTER_TEST(ar_flat_wide_6_10, gpu_raster_phase17,
371 drawAR_FLAT_WIDE();
373)
CESTER_BODY(static int s_got40;static int s_got80;static uint32_t s_cause;static uint32_t s_epc;static uint32_t s_from;static uint32_t *s_resume;static uint32_t *s_regs;static uint32_t(*s_customhandler)()=NULL;static uint32_t s_oldIMASK;static uint32_t s_oldDPCR;static uint32_t s_oldDICR;uint32_t handler(uint32_t *regs, uint32_t from) { if(from==0x40) s_got40=1;if(from==0x80) s_got80=1;uint32_t cause;uint32_t epc;s_from=from;asm("mfc0 %0, $13\nnop\nmfc0 %1, $14\nnop" :"=r"(cause), "=r"(epc));s_cause=cause;s_epc=epc;if(s_customhandler) { return s_customhandler();} else { return s_resume ?((uint32_t) s_resume) :(epc+4);} } void installExceptionHandlers(uint32_t(*handler)(uint32_t *regs, uint32_t from));void uninstallExceptionHandlers();uint32_t branchbranch1();uint32_t branchbranch2();uint32_t jumpjump1();uint32_t jumpjump2();uint32_t cpu_LWR_LWL_half(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_nodelay(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_delayed(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_load_different(uint32_t buff[], uint32_t initial);uint32_t cpu_LW_LWR(uint32_t buff[], uint32_t initial);uint32_t cpu_delayed_load(uint32_t buff[], uint32_t override);uint32_t cpu_delayed_load_cancelled(uint32_t buff[], uint32_t override);uint64_t cpu_delayed_load_load(uint32_t buff[], uint32_t override);uint32_t linkandload();uint32_t lwandlink();uint32_t nolink();static int s_interruptsWereEnabled;) CESTER_BEFORE_EACH(cpu_tests
CESTER_TEST(cpu_cop0_basic_write_bp, cpu_tests, uint32_t expectedEPC;uint32_t t;volatile uint32_t *ptr=(volatile uint32_t *) 0x58; *ptr=1;__asm__ volatile("" " lui %0, 0b1100101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0xfffffff0\n" " mtc0 %0, $9\n" :"=r"(t));cester_assert_uint_eq(1, *ptr);__asm__ volatile("la %0, 1f\n1:\nsw $0, 0x58($0)" :"=r"(expectedEPC));__asm__ volatile("mtc0 $0, $7\n");cester_assert_uint_eq(0, *ptr);cester_assert_uint_eq(1, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0x40, s_from);cester_assert_uint_eq(expectedEPC, s_epc);) CESTER_TEST(cpu_cop0_kseg_write_bp
#define EXPECT_AR_NARROW_TALL_11_20
Definition raster-expected-phase17.h:161
#define EXPECT_AR_STRETCH_8_8
Definition raster-expected-phase17.h:120
#define EXPECT_AR_COMPRESS_30_5
Definition raster-expected-phase17.h:109
#define EXPECT_AR_AXIS_BASE_10_8
Definition raster-expected-phase17.h:95
#define EXPECT_AR_STRETCH_6_6
Definition raster-expected-phase17.h:118
#define EXPECT_AR_NARROW_TALL_11_8
Definition raster-expected-phase17.h:159
#define EXPECT_AR_FLAT_WIDE_30_9
Definition raster-expected-phase17.h:171
#define EXPECT_AR_TWIST_45_8_8
Definition raster-expected-phase17.h:141
#define EXPECT_AR_NATURAL_18_15
Definition raster-expected-phase17.h:150
#define EXPECT_AR_FLAT_WIDE_6_10
Definition raster-expected-phase17.h:172
#define EXPECT_AR_STRETCH_10_7
Definition raster-expected-phase17.h:119
#define EXPECT_AR_AXIS_BASE_25_5
Definition raster-expected-phase17.h:99
#define EXPECT_AR_NATURAL_10_18
Definition raster-expected-phase17.h:151
#define EXPECT_AR_AXIS_BASE_20_6
Definition raster-expected-phase17.h:96
#define EXPECT_AR_NATURAL_5_5
Definition raster-expected-phase17.h:152
#define EXPECT_AR_TWIST_90_10_10
Definition raster-expected-phase17.h:129
#define EXPECT_AR_TWIST_45_12_12
Definition raster-expected-phase17.h:142
#define EXPECT_AR_FLAT_WIDE_8_9
Definition raster-expected-phase17.h:169
#define EXPECT_AR_AXIS_BASE_8_12
Definition raster-expected-phase17.h:97
#define EXPECT_AR_FLAT_WIDE_20_9
Definition raster-expected-phase17.h:170
#define EXPECT_AR_NARROW_TALL_12_14
Definition raster-expected-phase17.h:160
#define EXPECT_AR_AXIS_BASE_24_5
Definition raster-expected-phase17.h:98
#define EXPECT_AR_NARROW_TALL_13_6
Definition raster-expected-phase17.h:162
#define EXPECT_AR_COMPRESS_15_10
Definition raster-expected-phase17.h:108
#define EXPECT_AR_TWIST_45_12_4
Definition raster-expected-phase17.h:139
#define EXPECT_AR_TWIST_90_10_6
Definition raster-expected-phase17.h:131
#define EXPECT_AR_COMPRESS_10_7
Definition raster-expected-phase17.h:106
#define EXPECT_AR_NATURAL_12_10
Definition raster-expected-phase17.h:149
#define EXPECT_AR_TWIST_90_4_4
Definition raster-expected-phase17.h:132
#define EXPECT_AR_TWIST_45_4_12
Definition raster-expected-phase17.h:140
#define EXPECT_AR_COMPRESS_20_8
Definition raster-expected-phase17.h:107
#define EXPECT_AR_STRETCH_5_5
Definition raster-expected-phase17.h:121
#define EXPECT_AR_TWIST_90_6_10
Definition raster-expected-phase17.h:130
#define TEX17_TY
Definition texture-fixture-phase17.h:58
#define TEX17_TPAGE
Definition texture-fixture-phase17.h:65
#define TEX17_TX
Definition texture-fixture-phase17.h:57
#define PHASE17_ASSERT_PIXEL_EQ(expected, x_, y_)
Definition texture-fixture-phase17.h:102
#define TEX17_CLUT_FIELD
Definition texture-fixture-phase17.h:66
#define TEX_MOD_NEUTRAL
Definition texture-fixtures.h:328