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spu-adsr-edge.c
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1/*
2MIT License
3
4Copyright (c) 2026 PCSX-Redux authors
5
6Permission is hereby granted, free of charge, to any person obtaining a copy
7of this software and associated documentation files (the "Software"), to deal
8in the Software without restriction, including without limitation the rights
9to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10copies of the Software, and to permit persons to whom the Software is
11furnished to do so, subject to the following conditions:
12
13The above copyright notice and this permission notice shall be included in all
14copies or substantial portions of the Software.
15
16THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22SOFTWARE.
23
24*/
25
26// Hardware-first ADSR edge characterization.
27//
28// These tests intentionally do not derive expected values from psx-spx.
29// The first silicon run prints OBS lines for each trace summary; after those
30// values are baked into the macros below, the same traces become regression
31// assertions. One summary is deliberately compact: first sample, last sample,
32// min/max pair, and an FNV-style hash over the sampled ENVX trace.
33
34#define SPU_ADSR_EDGE_EXPECTED_UNSET 0xffffffffu
35
36#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_FIRST
37#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
38#endif
39#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_LAST
40#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
41#endif
42#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_MINMAX
43#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
44#endif
45#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_HASH
46#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
47#endif
48#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_FIRST
49#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
50#endif
51#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_LAST
52#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
53#endif
54#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_MINMAX
55#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
56#endif
57#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_HASH
58#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
59#endif
60#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_FIRST
61#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
62#endif
63#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_LAST
64#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
65#endif
66#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_MINMAX
67#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
68#endif
69#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_HASH
70#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
71#endif
72#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_FIRST
73#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
74#endif
75#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_LAST
76#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
77#endif
78#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_MINMAX
79#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
80#endif
81#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_HASH
82#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
83#endif
84#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_FIRST
85#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
86#endif
87#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_LAST
88#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
89#endif
90#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_MINMAX
91#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
92#endif
93#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_HASH
94#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
95#endif
96#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_FIRST
97#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
98#endif
99#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_LAST
100#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
101#endif
102#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_MINMAX
103#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
104#endif
105#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_HASH
106#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
107#endif
108#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_FIRST
109#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
110#endif
111#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_LAST
112#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
113#endif
114#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_MINMAX
115#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
116#endif
117#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_HASH
118#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
119#endif
120#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_FIRST
121#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
122#endif
123#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_LAST
124#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
125#endif
126#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_MINMAX
127#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
128#endif
129#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_HASH
130#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
131#endif
132#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_FIRST
133#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
134#endif
135#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_LAST
136#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
137#endif
138#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_MINMAX
139#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
140#endif
141#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_HASH
142#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
143#endif
144#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_FIRST
145#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
146#endif
147#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_LAST
148#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
149#endif
150#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_MINMAX
151#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
152#endif
153#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_HASH
154#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
155#endif
156#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_FIRST
157#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
158#endif
159#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_LAST
160#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
161#endif
162#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_MINMAX
163#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
164#endif
165#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_HASH
166#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
167#endif
168#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_FIRST
169#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
170#endif
171#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_LAST
172#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
173#endif
174#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_MINMAX
175#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
176#endif
177#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_HASH
178#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
179#endif
180#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_FIRST
181#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
182#endif
183#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_LAST
184#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
185#endif
186#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_MINMAX
187#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
188#endif
189#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_HASH
190#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
191#endif
192#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_FIRST
193#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
194#endif
195#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_LAST
196#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
197#endif
198#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_MINMAX
199#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
200#endif
201#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_HASH
202#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
203#endif
204#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_FIRST
205#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
206#endif
207#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_LAST
208#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
209#endif
210#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_MINMAX
211#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
212#endif
213#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_HASH
214#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
215#endif
216#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_FIRST
217#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
218#endif
219#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_LAST
220#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
221#endif
222#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_MINMAX
223#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
224#endif
225#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_HASH
226#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
227#endif
228#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_FIRST
229#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
230#endif
231#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_LAST
232#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
233#endif
234#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_MINMAX
235#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
236#endif
237#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_HASH
238#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
239#endif
240#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_FIRST
241#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
242#endif
243#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_LAST
244#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
245#endif
246#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_MINMAX
247#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
248#endif
249#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_HASH
250#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
251#endif
252#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_FIRST
253#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
254#endif
255#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_LAST
256#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
257#endif
258#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_MINMAX
259#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
260#endif
261#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_HASH
262#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
263#endif
264#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_FIRST
265#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
266#endif
267#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_LAST
268#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
269#endif
270#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_MINMAX
271#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
272#endif
273#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_HASH
274#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
275#endif
276#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_FIRST
277#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
278#endif
279#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_LAST
280#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
281#endif
282#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_MINMAX
283#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
284#endif
285#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_HASH
286#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
287#endif
288#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_FIRST
289#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
290#endif
291#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_LAST
292#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
293#endif
294#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_MINMAX
295#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
296#endif
297#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_HASH
298#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
299#endif
300#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_FIRST
301#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
302#endif
303#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_LAST
304#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
305#endif
306#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_MINMAX
307#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
308#endif
309#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_HASH
310#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
311#endif
312#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_FIRST
313#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
314#endif
315#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_LAST
316#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
317#endif
318#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_MINMAX
319#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
320#endif
321#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_HASH
322#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
323#endif
324#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_FIRST
325#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
326#endif
327#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_LAST
328#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
329#endif
330#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_MINMAX
331#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
332#endif
333#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_HASH
334#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
335#endif
336#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_FIRST
337#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
338#endif
339#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_LAST
340#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
341#endif
342#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_MINMAX
343#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
344#endif
345#ifndef SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_HASH
346#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
347#endif
348#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_00_FIRST
349#define SPU_ADSR_EDGE_EXPECTED_DECAY_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
350#endif
351#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_00_LAST
352#define SPU_ADSR_EDGE_EXPECTED_DECAY_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
353#endif
354#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_00_MINMAX
355#define SPU_ADSR_EDGE_EXPECTED_DECAY_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
356#endif
357#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_00_HASH
358#define SPU_ADSR_EDGE_EXPECTED_DECAY_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
359#endif
360#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_01_FIRST
361#define SPU_ADSR_EDGE_EXPECTED_DECAY_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
362#endif
363#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_01_LAST
364#define SPU_ADSR_EDGE_EXPECTED_DECAY_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
365#endif
366#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_01_MINMAX
367#define SPU_ADSR_EDGE_EXPECTED_DECAY_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
368#endif
369#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_01_HASH
370#define SPU_ADSR_EDGE_EXPECTED_DECAY_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
371#endif
372#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_02_FIRST
373#define SPU_ADSR_EDGE_EXPECTED_DECAY_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
374#endif
375#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_02_LAST
376#define SPU_ADSR_EDGE_EXPECTED_DECAY_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
377#endif
378#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_02_MINMAX
379#define SPU_ADSR_EDGE_EXPECTED_DECAY_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
380#endif
381#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_02_HASH
382#define SPU_ADSR_EDGE_EXPECTED_DECAY_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
383#endif
384#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_08_FIRST
385#define SPU_ADSR_EDGE_EXPECTED_DECAY_08_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
386#endif
387#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_08_LAST
388#define SPU_ADSR_EDGE_EXPECTED_DECAY_08_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
389#endif
390#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_08_MINMAX
391#define SPU_ADSR_EDGE_EXPECTED_DECAY_08_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
392#endif
393#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_08_HASH
394#define SPU_ADSR_EDGE_EXPECTED_DECAY_08_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
395#endif
396#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0A_FIRST
397#define SPU_ADSR_EDGE_EXPECTED_DECAY_0A_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
398#endif
399#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0A_LAST
400#define SPU_ADSR_EDGE_EXPECTED_DECAY_0A_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
401#endif
402#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0A_MINMAX
403#define SPU_ADSR_EDGE_EXPECTED_DECAY_0A_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
404#endif
405#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0A_HASH
406#define SPU_ADSR_EDGE_EXPECTED_DECAY_0A_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
407#endif
408#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0C_FIRST
409#define SPU_ADSR_EDGE_EXPECTED_DECAY_0C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
410#endif
411#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0C_LAST
412#define SPU_ADSR_EDGE_EXPECTED_DECAY_0C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
413#endif
414#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0C_MINMAX
415#define SPU_ADSR_EDGE_EXPECTED_DECAY_0C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
416#endif
417#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0C_HASH
418#define SPU_ADSR_EDGE_EXPECTED_DECAY_0C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
419#endif
420#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0E_FIRST
421#define SPU_ADSR_EDGE_EXPECTED_DECAY_0E_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
422#endif
423#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0E_LAST
424#define SPU_ADSR_EDGE_EXPECTED_DECAY_0E_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
425#endif
426#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0E_MINMAX
427#define SPU_ADSR_EDGE_EXPECTED_DECAY_0E_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
428#endif
429#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0E_HASH
430#define SPU_ADSR_EDGE_EXPECTED_DECAY_0E_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
431#endif
432#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0F_FIRST
433#define SPU_ADSR_EDGE_EXPECTED_DECAY_0F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
434#endif
435#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0F_LAST
436#define SPU_ADSR_EDGE_EXPECTED_DECAY_0F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
437#endif
438#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0F_MINMAX
439#define SPU_ADSR_EDGE_EXPECTED_DECAY_0F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
440#endif
441#ifndef SPU_ADSR_EDGE_EXPECTED_DECAY_0F_HASH
442#define SPU_ADSR_EDGE_EXPECTED_DECAY_0F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
443#endif
444#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_FIRST
445#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
446#endif
447#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_LAST
448#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
449#endif
450#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_MINMAX
451#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
452#endif
453#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_HASH
454#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
455#endif
456#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_FIRST
457#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
458#endif
459#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_LAST
460#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
461#endif
462#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_MINMAX
463#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
464#endif
465#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_HASH
466#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
467#endif
468#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_FIRST
469#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
470#endif
471#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_LAST
472#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
473#endif
474#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_MINMAX
475#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
476#endif
477#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_HASH
478#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
479#endif
480#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_FIRST
481#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
482#endif
483#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_LAST
484#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
485#endif
486#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_MINMAX
487#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
488#endif
489#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_HASH
490#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
491#endif
492#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_FIRST
493#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
494#endif
495#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_LAST
496#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
497#endif
498#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_MINMAX
499#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
500#endif
501#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_HASH
502#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
503#endif
504#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_FIRST
505#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
506#endif
507#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_LAST
508#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
509#endif
510#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_MINMAX
511#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
512#endif
513#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_HASH
514#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
515#endif
516#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_FIRST
517#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
518#endif
519#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_LAST
520#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
521#endif
522#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_MINMAX
523#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
524#endif
525#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_HASH
526#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
527#endif
528#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_FIRST
529#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
530#endif
531#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_LAST
532#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
533#endif
534#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_MINMAX
535#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
536#endif
537#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_HASH
538#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
539#endif
540#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_FIRST
541#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
542#endif
543#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_LAST
544#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
545#endif
546#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_MINMAX
547#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
548#endif
549#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_HASH
550#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
551#endif
552#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_FIRST
553#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
554#endif
555#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_LAST
556#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
557#endif
558#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_MINMAX
559#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
560#endif
561#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_HASH
562#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
563#endif
564#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_FIRST
565#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
566#endif
567#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_LAST
568#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
569#endif
570#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_MINMAX
571#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
572#endif
573#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_HASH
574#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
575#endif
576#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_FIRST
577#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
578#endif
579#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_LAST
580#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
581#endif
582#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_MINMAX
583#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
584#endif
585#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_HASH
586#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
587#endif
588#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_FIRST
589#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
590#endif
591#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_LAST
592#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
593#endif
594#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_MINMAX
595#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
596#endif
597#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_HASH
598#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
599#endif
600#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_FIRST
601#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
602#endif
603#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_LAST
604#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
605#endif
606#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_MINMAX
607#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
608#endif
609#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_HASH
610#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
611#endif
612#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_FIRST
613#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
614#endif
615#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_LAST
616#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
617#endif
618#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_MINMAX
619#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
620#endif
621#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_HASH
622#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
623#endif
624#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_FIRST
625#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
626#endif
627#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_LAST
628#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
629#endif
630#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_MINMAX
631#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
632#endif
633#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_HASH
634#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
635#endif
636#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_FIRST
637#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
638#endif
639#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_LAST
640#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
641#endif
642#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_MINMAX
643#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
644#endif
645#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_HASH
646#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
647#endif
648#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_FIRST
649#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
650#endif
651#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_LAST
652#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
653#endif
654#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_MINMAX
655#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
656#endif
657#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_HASH
658#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
659#endif
660#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_FIRST
661#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
662#endif
663#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_LAST
664#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
665#endif
666#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_MINMAX
667#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
668#endif
669#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_HASH
670#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
671#endif
672#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_FIRST
673#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
674#endif
675#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_LAST
676#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
677#endif
678#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_MINMAX
679#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
680#endif
681#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_HASH
682#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
683#endif
684#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_FIRST
685#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
686#endif
687#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_LAST
688#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
689#endif
690#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_MINMAX
691#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
692#endif
693#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_HASH
694#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
695#endif
696#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_FIRST
697#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
698#endif
699#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_LAST
700#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
701#endif
702#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_MINMAX
703#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
704#endif
705#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_HASH
706#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
707#endif
708#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_FIRST
709#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
710#endif
711#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_LAST
712#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
713#endif
714#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_MINMAX
715#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
716#endif
717#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_HASH
718#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
719#endif
720#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_FIRST
721#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
722#endif
723#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_LAST
724#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
725#endif
726#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_MINMAX
727#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
728#endif
729#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_HASH
730#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
731#endif
732#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_FIRST
733#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
734#endif
735#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_LAST
736#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
737#endif
738#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_MINMAX
739#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
740#endif
741#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_HASH
742#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
743#endif
744#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_FIRST
745#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
746#endif
747#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_LAST
748#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
749#endif
750#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_MINMAX
751#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
752#endif
753#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_HASH
754#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
755#endif
756#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_FIRST
757#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
758#endif
759#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_LAST
760#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
761#endif
762#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_MINMAX
763#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
764#endif
765#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_HASH
766#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
767#endif
768#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_FIRST
769#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
770#endif
771#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_LAST
772#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
773#endif
774#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_MINMAX
775#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
776#endif
777#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_HASH
778#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
779#endif
780#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_FIRST
781#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
782#endif
783#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_LAST
784#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
785#endif
786#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_MINMAX
787#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
788#endif
789#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_HASH
790#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
791#endif
792#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_FIRST
793#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
794#endif
795#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_LAST
796#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
797#endif
798#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_MINMAX
799#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
800#endif
801#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_HASH
802#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
803#endif
804#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_FIRST
805#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
806#endif
807#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_LAST
808#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
809#endif
810#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_MINMAX
811#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
812#endif
813#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_HASH
814#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
815#endif
816#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_FIRST
817#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
818#endif
819#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_LAST
820#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
821#endif
822#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_MINMAX
823#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
824#endif
825#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_HASH
826#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
827#endif
828#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_FIRST
829#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
830#endif
831#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_LAST
832#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
833#endif
834#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_MINMAX
835#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
836#endif
837#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_HASH
838#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
839#endif
840#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_FIRST
841#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
842#endif
843#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_LAST
844#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
845#endif
846#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_MINMAX
847#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
848#endif
849#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_HASH
850#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
851#endif
852#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_FIRST
853#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
854#endif
855#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_LAST
856#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
857#endif
858#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_MINMAX
859#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
860#endif
861#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_HASH
862#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
863#endif
864#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_FIRST
865#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
866#endif
867#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_LAST
868#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
869#endif
870#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_MINMAX
871#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
872#endif
873#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_HASH
874#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
875#endif
876#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_FIRST
877#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
878#endif
879#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_LAST
880#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
881#endif
882#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_MINMAX
883#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
884#endif
885#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_HASH
886#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
887#endif
888#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_FIRST
889#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
890#endif
891#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_LAST
892#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
893#endif
894#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_MINMAX
895#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
896#endif
897#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_HASH
898#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
899#endif
900#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_FIRST
901#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
902#endif
903#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_LAST
904#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
905#endif
906#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_MINMAX
907#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
908#endif
909#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_HASH
910#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
911#endif
912#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_FIRST
913#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
914#endif
915#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_LAST
916#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
917#endif
918#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_MINMAX
919#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
920#endif
921#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_HASH
922#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
923#endif
924#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_FIRST
925#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
926#endif
927#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_LAST
928#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
929#endif
930#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_MINMAX
931#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
932#endif
933#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_HASH
934#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
935#endif
936#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_FIRST
937#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
938#endif
939#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_LAST
940#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
941#endif
942#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_MINMAX
943#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
944#endif
945#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_HASH
946#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
947#endif
948#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_FIRST
949#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
950#endif
951#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_LAST
952#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
953#endif
954#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_MINMAX
955#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
956#endif
957#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_HASH
958#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
959#endif
960#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_FIRST
961#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
962#endif
963#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_LAST
964#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
965#endif
966#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_MINMAX
967#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
968#endif
969#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_HASH
970#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
971#endif
972#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_FIRST
973#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
974#endif
975#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_LAST
976#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
977#endif
978#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_MINMAX
979#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
980#endif
981#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_HASH
982#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
983#endif
984#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_FIRST
985#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
986#endif
987#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_LAST
988#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
989#endif
990#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_MINMAX
991#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
992#endif
993#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_HASH
994#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
995#endif
996#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_FIRST
997#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
998#endif
999#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_LAST
1000#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1001#endif
1002#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_MINMAX
1003#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1004#endif
1005#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_HASH
1006#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1007#endif
1008#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_FIRST
1009#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1010#endif
1011#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_LAST
1012#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1013#endif
1014#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_MINMAX
1015#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1016#endif
1017#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_HASH
1018#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1019#endif
1020#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_FIRST
1021#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1022#endif
1023#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_LAST
1024#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1025#endif
1026#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_MINMAX
1027#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1028#endif
1029#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_HASH
1030#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1031#endif
1032#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_FIRST
1033#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1034#endif
1035#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_LAST
1036#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1037#endif
1038#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_MINMAX
1039#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1040#endif
1041#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_HASH
1042#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1043#endif
1044#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_FIRST
1045#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1046#endif
1047#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_LAST
1048#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1049#endif
1050#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_MINMAX
1051#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1052#endif
1053#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_HASH
1054#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1055#endif
1056#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_FIRST
1057#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1058#endif
1059#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_LAST
1060#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1061#endif
1062#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_MINMAX
1063#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1064#endif
1065#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_HASH
1066#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1067#endif
1068#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_FIRST
1069#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1070#endif
1071#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_LAST
1072#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1073#endif
1074#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_MINMAX
1075#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1076#endif
1077#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_HASH
1078#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1079#endif
1080#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_FIRST
1081#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1082#endif
1083#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_LAST
1084#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1085#endif
1086#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_MINMAX
1087#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1088#endif
1089#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_HASH
1090#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1091#endif
1092#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_FIRST
1093#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1094#endif
1095#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_LAST
1096#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1097#endif
1098#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_MINMAX
1099#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1100#endif
1101#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_HASH
1102#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1103#endif
1104#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_FIRST
1105#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1106#endif
1107#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_LAST
1108#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1109#endif
1110#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_MINMAX
1111#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1112#endif
1113#ifndef SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_HASH
1114#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1115#endif
1116#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_FIRST
1117#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1118#endif
1119#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_LAST
1120#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1121#endif
1122#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_MINMAX
1123#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1124#endif
1125#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_HASH
1126#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1127#endif
1128#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_FIRST
1129#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1130#endif
1131#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_LAST
1132#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1133#endif
1134#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_MINMAX
1135#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1136#endif
1137#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_HASH
1138#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1139#endif
1140#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_FIRST
1141#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1142#endif
1143#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_LAST
1144#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1145#endif
1146#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_MINMAX
1147#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1148#endif
1149#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_HASH
1150#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1151#endif
1152#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_FIRST
1153#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1154#endif
1155#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_LAST
1156#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1157#endif
1158#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_MINMAX
1159#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1160#endif
1161#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_HASH
1162#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1163#endif
1164#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_FIRST
1165#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1166#endif
1167#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_LAST
1168#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1169#endif
1170#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_MINMAX
1171#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1172#endif
1173#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_HASH
1174#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1175#endif
1176#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_FIRST
1177#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1178#endif
1179#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_LAST
1180#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1181#endif
1182#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_MINMAX
1183#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1184#endif
1185#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_HASH
1186#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1187#endif
1188#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_FIRST
1189#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1190#endif
1191#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_LAST
1192#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1193#endif
1194#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_MINMAX
1195#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1196#endif
1197#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_HASH
1198#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1199#endif
1200#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_FIRST
1201#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1202#endif
1203#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_LAST
1204#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1205#endif
1206#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_MINMAX
1207#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1208#endif
1209#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_HASH
1210#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1211#endif
1212#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_FIRST
1213#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1214#endif
1215#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_LAST
1216#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1217#endif
1218#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_MINMAX
1219#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1220#endif
1221#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_HASH
1222#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1223#endif
1224#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_FIRST
1225#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1226#endif
1227#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_LAST
1228#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1229#endif
1230#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_MINMAX
1231#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1232#endif
1233#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_HASH
1234#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1235#endif
1236#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_FIRST
1237#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1238#endif
1239#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_LAST
1240#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1241#endif
1242#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_MINMAX
1243#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1244#endif
1245#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_HASH
1246#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1247#endif
1248#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_FIRST
1249#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1250#endif
1251#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_LAST
1252#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1253#endif
1254#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_MINMAX
1255#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1256#endif
1257#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_HASH
1258#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1259#endif
1260#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_FIRST
1261#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1262#endif
1263#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_LAST
1264#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1265#endif
1266#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_MINMAX
1267#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1268#endif
1269#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_HASH
1270#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1271#endif
1272#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_FIRST
1273#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1274#endif
1275#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_LAST
1276#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1277#endif
1278#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_MINMAX
1279#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1280#endif
1281#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_HASH
1282#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1283#endif
1284#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_FIRST
1285#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1286#endif
1287#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_LAST
1288#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1289#endif
1290#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_MINMAX
1291#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1292#endif
1293#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_HASH
1294#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1295#endif
1296#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_FIRST
1297#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1298#endif
1299#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_LAST
1300#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1301#endif
1302#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_MINMAX
1303#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1304#endif
1305#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_HASH
1306#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1307#endif
1308#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_FIRST
1309#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1310#endif
1311#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_LAST
1312#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1313#endif
1314#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_MINMAX
1315#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1316#endif
1317#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_HASH
1318#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1319#endif
1320#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_FIRST
1321#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1322#endif
1323#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_LAST
1324#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1325#endif
1326#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_MINMAX
1327#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1328#endif
1329#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_HASH
1330#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1331#endif
1332#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_FIRST
1333#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1334#endif
1335#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_LAST
1336#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1337#endif
1338#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_MINMAX
1339#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1340#endif
1341#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_HASH
1342#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1343#endif
1344#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_FIRST
1345#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1346#endif
1347#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_LAST
1348#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1349#endif
1350#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_MINMAX
1351#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1352#endif
1353#ifndef SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_HASH
1354#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1355#endif
1356#ifndef SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_FIRST
1357#define SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1358#endif
1359#ifndef SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_LAST
1360#define SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1361#endif
1362#ifndef SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_MINMAX
1363#define SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1364#endif
1365#ifndef SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_HASH
1366#define SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1367#endif
1368#ifndef SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_FIRST
1369#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1370#endif
1371#ifndef SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_LAST
1372#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1373#endif
1374#ifndef SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_MINMAX
1375#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1376#endif
1377#ifndef SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_HASH
1378#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1379#endif
1380#ifndef SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_FIRST
1381#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1382#endif
1383#ifndef SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_LAST
1384#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1385#endif
1386#ifndef SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_MINMAX
1387#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1388#endif
1389#ifndef SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_HASH
1390#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1391#endif
1392#ifndef SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_FIRST
1393#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1394#endif
1395#ifndef SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_LAST
1396#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1397#endif
1398#ifndef SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_MINMAX
1399#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1400#endif
1401#ifndef SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_HASH
1402#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1403#endif
1404#ifndef SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_FIRST
1405#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET
1406#endif
1407#ifndef SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_LAST
1408#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_LAST SPU_ADSR_EDGE_EXPECTED_UNSET
1409#endif
1410#ifndef SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_MINMAX
1411#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET
1412#endif
1413#ifndef SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_HASH
1414#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_HASH SPU_ADSR_EDGE_EXPECTED_UNSET
1415#endif
1416
1417#ifndef SPU_ADSR_EDGE_MACROS_DEFINED
1418#define SPU_ADSR_EDGE_MACROS_DEFINED
1419#define ATTACK_RATE(rate, exp) ATTACK((rate) & 3, ((rate) >> 2) & 31, exp)
1420#define SUSTAIN_RATE(rate, level, direction, exp) SUSTAIN((rate) & 3, ((rate) >> 2) & 31, level, direction, exp)
1421#define RELEASE_RATE(rate, exp) RELEASE(((rate) >> 2) & 31, exp)
1422#define SPU_ADSR_EDGE_RUN(name, adsr, mode, samples, keyoff, first, last, minmax, hash) \
1423 spu_adsr_edge_run_trace(name, adsr, mode, samples, keyoff, first, last, minmax, hash)
1424#endif
1425
1426CESTER_BODY(
1427static uint32_t spu_adsr_edge_hash(const uint16_t *envx, unsigned samples) {
1428 uint32_t h = 2166136261u;
1429 for (unsigned i = 0; i < samples; i++) {
1430 h ^= envx[i];
1431 h *= 16777619u;
1432 h ^= i;
1433 h *= 16777619u;
1434 }
1435 return h;
1436}
1437
1438static uint32_t spu_adsr_edge_minmax(const uint16_t *envx, unsigned samples) {
1439 uint16_t min = envx[0];
1440 uint16_t max = envx[0];
1441 for (unsigned i = 1; i < samples; i++) {
1442 if (envx[i] < min) min = envx[i];
1443 if (envx[i] > max) max = envx[i];
1444 }
1445 return ((uint32_t)min << 16) | max;
1446}
1447
1448static void spu_adsr_edge_expect_u32(const char *trace, const char *field, uint32_t expected, uint32_t got) {
1449 if (expected == SPU_ADSR_EDGE_EXPECTED_UNSET) {
1450 ramsyscall_printf("OBS spu_adsr_edge expected %s_%s=0x%08lx\n", trace, field, (unsigned long)got);
1451 } else {
1452 cester_assert_uint_eq(expected, got);
1453 }
1454}
1455
1456static void spu_adsr_edge_capture_custom(const char *name, uint32_t adsr, uint8_t mode, uint8_t samples, uint8_t keyoffAt, uint16_t *envx) {
1457 switch (mode) {
1458 case 0:
1459 spu_adsr_capture(adsr, envx, samples);
1460 break;
1461 case 1:
1462 spu_adsr_capture_with_keyoff(adsr, envx, samples, keyoffAt);
1463 break;
1464 default:
1465 spu_reset_quiet();
1466 SPU_CTRL = 0x8000 | 0x4000;
1467 SPU_VOL_MAIN_LEFT = 0; SPU_VOL_MAIN_RIGHT = 0;
1468 SPU_VOICES[1].sampleRate = 0x1000;
1469 SPU_VOICES[1].sampleStartAddr = SPU_UPLOAD_ADDR >> 3;
1470 SPU_VOICES[1].sampleRepeatAddr = SPU_UPLOAD_ADDR >> 3;
1471 SPU_VOICES[1].volumeLeft = 0;
1472 SPU_VOICES[1].volumeRight = 0;
1473 SPU_VOICES[1].adsrHi = (uint16_t)(ATTACK_RATE(0x30, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0));
1474 SPU_VOICES[1].adsrLo = (uint16_t)((SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x30, 0)) >> 16);
1475 SPU_KEY_OFF_LOW = 0xffff; SPU_KEY_OFF_HIGH = 0xffff;
1476 spu_wait_status_bit11_flip();
1477 envx[0] = SPU_VOICES[1].currentVolume;
1478 SPU_KEY_OFF_LOW = 0; SPU_KEY_OFF_HIGH = 0;
1479 SPU_KEY_ON_LOW = 1u << 1;
1480 envx[1] = SPU_VOICES[1].currentVolume;
1481 for (unsigned i = 2; i < samples; i++) {
1482 spu_wait_status_bit11_flip();
1483 if (name[0] == 'm' && i == 4) SPU_VOICES[1].currentVolume = (name[12] == 'z') ? 0 : 0x7fff;
1484 if (name[0] == 'b' && name[9] == 'r' && i == 4) SPU_KEY_OFF_LOW = 1u << 1;
1485 envx[i] = SPU_VOICES[1].currentVolume;
1486 }
1487 SPU_KEY_OFF_LOW = 0xffff; SPU_KEY_OFF_HIGH = 0xffff;
1488 muteSpu();
1489 break;
1490 }
1491}
1492
1493static void spu_adsr_edge_run_trace(const char *name, uint32_t adsr, uint8_t mode, uint8_t samples, uint8_t keyoffAt, uint32_t expectedFirst, uint32_t expectedLast, uint32_t expectedMinMax, uint32_t expectedHash) {
1494 uint16_t envx[64];
1495 spu_adsr_edge_capture_custom(name, adsr, mode, samples, keyoffAt, envx);
1496 spu_adsr_edge_expect_u32(name, "FIRST", expectedFirst, envx[0]);
1497 spu_adsr_edge_expect_u32(name, "LAST", expectedLast, envx[samples - 1]);
1498 spu_adsr_edge_expect_u32(name, "MINMAX", expectedMinMax, spu_adsr_edge_minmax(envx, samples));
1499 spu_adsr_edge_expect_u32(name, "HASH", expectedHash, spu_adsr_edge_hash(envx, samples));
1500}
1501)
1502
1503CESTER_TEST(adsr_edge_characterization_traces, spu_tests,
1504 SPU_ADSR_EDGE_RUN("attack_lin_00", ATTACK_RATE(0x00, 0) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_HASH);
1505 SPU_ADSR_EDGE_RUN("attack_lin_01", ATTACK_RATE(0x01, 0) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_HASH);
1506 SPU_ADSR_EDGE_RUN("attack_lin_02", ATTACK_RATE(0x02, 0) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_HASH);
1507 SPU_ADSR_EDGE_RUN("attack_lin_03", ATTACK_RATE(0x03, 0) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_HASH);
1508 SPU_ADSR_EDGE_RUN("attack_lin_04", ATTACK_RATE(0x04, 0) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_HASH);
1509 SPU_ADSR_EDGE_RUN("attack_lin_24", ATTACK_RATE(0x24, 0) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_HASH);
1510 SPU_ADSR_EDGE_RUN("attack_lin_28", ATTACK_RATE(0x28, 0) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_HASH);
1511 SPU_ADSR_EDGE_RUN("attack_lin_2c", ATTACK_RATE(0x2c, 0) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_HASH);
1512 SPU_ADSR_EDGE_RUN("attack_lin_30", ATTACK_RATE(0x30, 0) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_HASH);
1513 SPU_ADSR_EDGE_RUN("attack_lin_34", ATTACK_RATE(0x34, 0) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_HASH);
1514 SPU_ADSR_EDGE_RUN("attack_lin_40", ATTACK_RATE(0x40, 0) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_HASH);
1515 SPU_ADSR_EDGE_RUN("attack_lin_60", ATTACK_RATE(0x60, 0) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_HASH);
1516 SPU_ADSR_EDGE_RUN("attack_lin_7f", ATTACK_RATE(0x7f, 0) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_HASH);
1517 SPU_ADSR_EDGE_RUN("attack_exp_00", ATTACK_RATE(0x00, 1) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_HASH);
1518 SPU_ADSR_EDGE_RUN("attack_exp_01", ATTACK_RATE(0x01, 1) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_HASH);
1519 SPU_ADSR_EDGE_RUN("attack_exp_02", ATTACK_RATE(0x02, 1) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_HASH);
1520 SPU_ADSR_EDGE_RUN("attack_exp_03", ATTACK_RATE(0x03, 1) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_HASH);
1521 SPU_ADSR_EDGE_RUN("attack_exp_04", ATTACK_RATE(0x04, 1) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_HASH);
1522 SPU_ADSR_EDGE_RUN("attack_exp_24", ATTACK_RATE(0x24, 1) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_HASH);
1523 SPU_ADSR_EDGE_RUN("attack_exp_28", ATTACK_RATE(0x28, 1) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_HASH);
1524 SPU_ADSR_EDGE_RUN("attack_exp_2c", ATTACK_RATE(0x2c, 1) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_HASH);
1525 SPU_ADSR_EDGE_RUN("attack_exp_30", ATTACK_RATE(0x30, 1) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_HASH);
1526 SPU_ADSR_EDGE_RUN("attack_exp_34", ATTACK_RATE(0x34, 1) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_HASH);
1527 SPU_ADSR_EDGE_RUN("attack_exp_40", ATTACK_RATE(0x40, 1) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_HASH);
1528 SPU_ADSR_EDGE_RUN("attack_exp_60", ATTACK_RATE(0x60, 1) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_HASH);
1529 SPU_ADSR_EDGE_RUN("attack_exp_7f", ATTACK_RATE(0x7f, 1) | DECAY(15) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_FIRST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_LAST, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_MINMAX, SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_HASH);
1530 SPU_ADSR_EDGE_RUN("decay_00", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 0, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_DECAY_00_FIRST, SPU_ADSR_EDGE_EXPECTED_DECAY_00_LAST, SPU_ADSR_EDGE_EXPECTED_DECAY_00_MINMAX, SPU_ADSR_EDGE_EXPECTED_DECAY_00_HASH);
1531 SPU_ADSR_EDGE_RUN("decay_01", ATTACK_RATE(0x00, 0) | DECAY(1) | SUSTAIN(3, 31, 0, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_DECAY_01_FIRST, SPU_ADSR_EDGE_EXPECTED_DECAY_01_LAST, SPU_ADSR_EDGE_EXPECTED_DECAY_01_MINMAX, SPU_ADSR_EDGE_EXPECTED_DECAY_01_HASH);
1532 SPU_ADSR_EDGE_RUN("decay_02", ATTACK_RATE(0x00, 0) | DECAY(2) | SUSTAIN(3, 31, 0, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_DECAY_02_FIRST, SPU_ADSR_EDGE_EXPECTED_DECAY_02_LAST, SPU_ADSR_EDGE_EXPECTED_DECAY_02_MINMAX, SPU_ADSR_EDGE_EXPECTED_DECAY_02_HASH);
1533 SPU_ADSR_EDGE_RUN("decay_08", ATTACK_RATE(0x00, 0) | DECAY(8) | SUSTAIN(3, 31, 0, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_DECAY_08_FIRST, SPU_ADSR_EDGE_EXPECTED_DECAY_08_LAST, SPU_ADSR_EDGE_EXPECTED_DECAY_08_MINMAX, SPU_ADSR_EDGE_EXPECTED_DECAY_08_HASH);
1534 SPU_ADSR_EDGE_RUN("decay_0a", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 0, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_DECAY_0A_FIRST, SPU_ADSR_EDGE_EXPECTED_DECAY_0A_LAST, SPU_ADSR_EDGE_EXPECTED_DECAY_0A_MINMAX, SPU_ADSR_EDGE_EXPECTED_DECAY_0A_HASH);
1535 SPU_ADSR_EDGE_RUN("decay_0c", ATTACK_RATE(0x00, 0) | DECAY(12) | SUSTAIN(3, 31, 0, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_DECAY_0C_FIRST, SPU_ADSR_EDGE_EXPECTED_DECAY_0C_LAST, SPU_ADSR_EDGE_EXPECTED_DECAY_0C_MINMAX, SPU_ADSR_EDGE_EXPECTED_DECAY_0C_HASH);
1536 SPU_ADSR_EDGE_RUN("decay_0e", ATTACK_RATE(0x00, 0) | DECAY(14) | SUSTAIN(3, 31, 0, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_DECAY_0E_FIRST, SPU_ADSR_EDGE_EXPECTED_DECAY_0E_LAST, SPU_ADSR_EDGE_EXPECTED_DECAY_0E_MINMAX, SPU_ADSR_EDGE_EXPECTED_DECAY_0E_HASH);
1537 SPU_ADSR_EDGE_RUN("decay_0f", ATTACK_RATE(0x00, 0) | DECAY(15) | SUSTAIN(3, 31, 0, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_DECAY_0F_FIRST, SPU_ADSR_EDGE_EXPECTED_DECAY_0F_LAST, SPU_ADSR_EDGE_EXPECTED_DECAY_0F_MINMAX, SPU_ADSR_EDGE_EXPECTED_DECAY_0F_HASH);
1538 SPU_ADSR_EDGE_RUN("sustain_level_00", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 0, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_HASH);
1539 SPU_ADSR_EDGE_RUN("sustain_level_01", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 1, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_HASH);
1540 SPU_ADSR_EDGE_RUN("sustain_level_02", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 2, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_HASH);
1541 SPU_ADSR_EDGE_RUN("sustain_level_03", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 3, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_HASH);
1542 SPU_ADSR_EDGE_RUN("sustain_level_04", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 4, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_HASH);
1543 SPU_ADSR_EDGE_RUN("sustain_level_05", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 5, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_HASH);
1544 SPU_ADSR_EDGE_RUN("sustain_level_06", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 6, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_HASH);
1545 SPU_ADSR_EDGE_RUN("sustain_level_07", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 7, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_HASH);
1546 SPU_ADSR_EDGE_RUN("sustain_level_08", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 8, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_HASH);
1547 SPU_ADSR_EDGE_RUN("sustain_level_09", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 9, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_HASH);
1548 SPU_ADSR_EDGE_RUN("sustain_level_0a", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 10, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_HASH);
1549 SPU_ADSR_EDGE_RUN("sustain_level_0b", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 11, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_HASH);
1550 SPU_ADSR_EDGE_RUN("sustain_level_0c", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 12, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_HASH);
1551 SPU_ADSR_EDGE_RUN("sustain_level_0d", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 13, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_HASH);
1552 SPU_ADSR_EDGE_RUN("sustain_level_0e", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 14, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_HASH);
1553 SPU_ADSR_EDGE_RUN("sustain_level_0f", ATTACK_RATE(0x00, 0) | DECAY(10) | SUSTAIN(3, 31, 15, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 32, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_HASH);
1554 SPU_ADSR_EDGE_RUN("sustain_up_lin_00", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x00, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_HASH);
1555 SPU_ADSR_EDGE_RUN("sustain_up_lin_01", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x01, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_HASH);
1556 SPU_ADSR_EDGE_RUN("sustain_up_lin_02", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x02, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_HASH);
1557 SPU_ADSR_EDGE_RUN("sustain_up_lin_03", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x03, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_HASH);
1558 SPU_ADSR_EDGE_RUN("sustain_up_lin_2c", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x2c, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_HASH);
1559 SPU_ADSR_EDGE_RUN("sustain_up_lin_30", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x30, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_HASH);
1560 SPU_ADSR_EDGE_RUN("sustain_up_lin_34", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x34, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_HASH);
1561 SPU_ADSR_EDGE_RUN("sustain_up_lin_40", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x40, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_HASH);
1562 SPU_ADSR_EDGE_RUN("sustain_up_lin_60", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x60, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_HASH);
1563 SPU_ADSR_EDGE_RUN("sustain_up_lin_7f", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x7f, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_HASH);
1564 SPU_ADSR_EDGE_RUN("sustain_up_exp_00", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x00, 15, 0, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_HASH);
1565 SPU_ADSR_EDGE_RUN("sustain_up_exp_01", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x01, 15, 0, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_HASH);
1566 SPU_ADSR_EDGE_RUN("sustain_up_exp_02", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x02, 15, 0, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_HASH);
1567 SPU_ADSR_EDGE_RUN("sustain_up_exp_03", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x03, 15, 0, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_HASH);
1568 SPU_ADSR_EDGE_RUN("sustain_up_exp_2c", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x2c, 15, 0, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_HASH);
1569 SPU_ADSR_EDGE_RUN("sustain_up_exp_30", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x30, 15, 0, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_HASH);
1570 SPU_ADSR_EDGE_RUN("sustain_up_exp_34", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x34, 15, 0, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_HASH);
1571 SPU_ADSR_EDGE_RUN("sustain_up_exp_40", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x40, 15, 0, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_HASH);
1572 SPU_ADSR_EDGE_RUN("sustain_up_exp_60", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x60, 15, 0, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_HASH);
1573 SPU_ADSR_EDGE_RUN("sustain_up_exp_7f", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x7f, 15, 0, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_HASH);
1574 SPU_ADSR_EDGE_RUN("sustain_down_lin_00", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x00, 15, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_HASH);
1575 SPU_ADSR_EDGE_RUN("sustain_down_lin_01", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x01, 15, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_HASH);
1576 SPU_ADSR_EDGE_RUN("sustain_down_lin_02", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x02, 15, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_HASH);
1577 SPU_ADSR_EDGE_RUN("sustain_down_lin_03", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x03, 15, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_HASH);
1578 SPU_ADSR_EDGE_RUN("sustain_down_lin_2c", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x2c, 15, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_HASH);
1579 SPU_ADSR_EDGE_RUN("sustain_down_lin_30", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x30, 15, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_HASH);
1580 SPU_ADSR_EDGE_RUN("sustain_down_lin_34", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x34, 15, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_HASH);
1581 SPU_ADSR_EDGE_RUN("sustain_down_lin_40", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x40, 15, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_HASH);
1582 SPU_ADSR_EDGE_RUN("sustain_down_lin_60", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x60, 15, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_HASH);
1583 SPU_ADSR_EDGE_RUN("sustain_down_lin_7f", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x7f, 15, 1, 0) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_HASH);
1584 SPU_ADSR_EDGE_RUN("sustain_down_exp_00", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x00, 15, 1, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_HASH);
1585 SPU_ADSR_EDGE_RUN("sustain_down_exp_01", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x01, 15, 1, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_HASH);
1586 SPU_ADSR_EDGE_RUN("sustain_down_exp_02", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x02, 15, 1, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_HASH);
1587 SPU_ADSR_EDGE_RUN("sustain_down_exp_03", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x03, 15, 1, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_HASH);
1588 SPU_ADSR_EDGE_RUN("sustain_down_exp_2c", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x2c, 15, 1, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_HASH);
1589 SPU_ADSR_EDGE_RUN("sustain_down_exp_30", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x30, 15, 1, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_HASH);
1590 SPU_ADSR_EDGE_RUN("sustain_down_exp_34", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x34, 15, 1, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_HASH);
1591 SPU_ADSR_EDGE_RUN("sustain_down_exp_40", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x40, 15, 1, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_HASH);
1592 SPU_ADSR_EDGE_RUN("sustain_down_exp_60", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x60, 15, 1, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_HASH);
1593 SPU_ADSR_EDGE_RUN("sustain_down_exp_7f", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN_RATE(0x7f, 15, 1, 1) | RELEASE_RATE(0x7f, 0), 0, 64, 0, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_FIRST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_LAST, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_MINMAX, SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_HASH);
1594 SPU_ADSR_EDGE_RUN("release_from_sustain_lin_00", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x00, 0), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_HASH);
1595 SPU_ADSR_EDGE_RUN("release_from_sustain_lin_01", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x01, 0), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_HASH);
1596 SPU_ADSR_EDGE_RUN("release_from_sustain_lin_02", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x02, 0), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_HASH);
1597 SPU_ADSR_EDGE_RUN("release_from_sustain_lin_03", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x03, 0), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_HASH);
1598 SPU_ADSR_EDGE_RUN("release_from_sustain_lin_2c", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x2c, 0), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_HASH);
1599 SPU_ADSR_EDGE_RUN("release_from_sustain_lin_30", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x30, 0), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_HASH);
1600 SPU_ADSR_EDGE_RUN("release_from_sustain_lin_34", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x34, 0), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_HASH);
1601 SPU_ADSR_EDGE_RUN("release_from_sustain_lin_40", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x40, 0), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_HASH);
1602 SPU_ADSR_EDGE_RUN("release_from_sustain_lin_60", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x60, 0), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_HASH);
1603 SPU_ADSR_EDGE_RUN("release_from_sustain_lin_7f", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 0), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_HASH);
1604 SPU_ADSR_EDGE_RUN("release_from_sustain_exp_00", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x00, 1), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_HASH);
1605 SPU_ADSR_EDGE_RUN("release_from_sustain_exp_01", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x01, 1), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_HASH);
1606 SPU_ADSR_EDGE_RUN("release_from_sustain_exp_02", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x02, 1), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_HASH);
1607 SPU_ADSR_EDGE_RUN("release_from_sustain_exp_03", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x03, 1), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_HASH);
1608 SPU_ADSR_EDGE_RUN("release_from_sustain_exp_2c", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x2c, 1), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_HASH);
1609 SPU_ADSR_EDGE_RUN("release_from_sustain_exp_30", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x30, 1), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_HASH);
1610 SPU_ADSR_EDGE_RUN("release_from_sustain_exp_34", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x34, 1), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_HASH);
1611 SPU_ADSR_EDGE_RUN("release_from_sustain_exp_40", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x40, 1), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_HASH);
1612 SPU_ADSR_EDGE_RUN("release_from_sustain_exp_60", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x60, 1), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_HASH);
1613 SPU_ADSR_EDGE_RUN("release_from_sustain_exp_7f", ATTACK_RATE(0x00, 0) | DECAY(0) | SUSTAIN(3, 31, 15, 0, 0) | RELEASE_RATE(0x7f, 1), 1, 64, 8, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_FIRST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_LAST, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_MINMAX, SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_HASH);
1614 SPU_ADSR_EDGE_RUN("timing_keyon_zero_start", 0, 2, 16, 0, SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_FIRST, SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_LAST, SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_MINMAX, SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_HASH);
1615 SPU_ADSR_EDGE_RUN("boundary_attack_peak", 0, 2, 16, 0, SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_FIRST, SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_LAST, SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_MINMAX, SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_HASH);
1616 SPU_ADSR_EDGE_RUN("boundary_release_zero", 0, 2, 16, 0, SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_FIRST, SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_LAST, SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_MINMAX, SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_HASH);
1617 SPU_ADSR_EDGE_RUN("manual_envx_zero_then_attack", 0, 2, 16, 0, SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_FIRST, SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_LAST, SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_MINMAX, SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_HASH);
1618 SPU_ADSR_EDGE_RUN("manual_envx_7fff_then_release", 0, 2, 16, 0, SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_FIRST, SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_LAST, SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_MINMAX, SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_HASH);
1619)
CESTER_TEST
CESTER_TEST(cdlGetLocL, test_instances, int resetDone=resetCDRom();if(!resetDone) { cester_assert_true(resetDone);return;} initializeTime();CDROM_REG0=0;CDROM_REG1=CDL_GETLOCL;uint32_t ackTime=waitCDRomIRQ();uint8_t cause1=ackCDRomCause();uint8_t ctrl1=CDROM_REG0 &~3;uint8_t response[16];uint8_t responseSize=readResponse(response);uint8_t ctrl2=CDROM_REG0 &~3;CDROM_REG0=1;uint8_t cause1b=CDROM_REG3_UC;cester_assert_uint_eq(3, cause1);cester_assert_uint_eq(0xe0, cause1b);cester_assert_uint_eq(0x38, ctrl1);cester_assert_uint_eq(0x18, ctrl2);cester_assert_uint_eq(8, responseSize);cester_assert_uint_ge(ackTime, 500);cester_assert_uint_lt(ackTime, 7000);ramsyscall_printf("Basic getlocL, ack in %ius\n", ackTime);) CESTER_TEST(cdlGetLocLafterSeekP
cester_assert_uint_eq
cester_assert_uint_eq(5, cause1)
CESTER_BODY
CESTER_BODY(static void hexdump(const void *data_, unsigned size) { const uint8_t *data=(const uint8_t *) data_;char ascii[17];ascii[16]=0;for(unsigned i=0;i< size;i++) { if(i % 16==0) ramsyscall_printf("%08x |", i);ramsyscall_printf("%02X ", data[i]);ascii[i % 16]=data[i] >=' ' &&data[i]<='~' ? data[i] :'.';unsigned j=i+1;if((j % 8==0)||(j==size)) { ramsyscall_printf(" ");if(j % 16==0) { ramsyscall_printf("| %s \n", ascii);} else if(j==size) { ascii[j % 16]=0;if(j % 16<=8) ramsyscall_printf(" ");for(j %=16;j< 16;j++) ramsyscall_printf(" ");ramsyscall_printf("| %s \n", ascii);} } } } static int s_interruptsWereEnabled=0;static uint16_t s_oldMode=0;static uint32_t s_lastHSyncCounter=0;static uint32_t s_currentTime=0;static uint32_t s_oldIMASK=0;static const unsigned US_PER_HBLANK=64;struct LocPResult { uint8_t track, index, m, s, f, am, as, af;uint8_t padding[8];};static uint8_t btoi(uint8_t b) { return(b > > 4) *10+(b &0xf);} static uint8_t itob(uint8_t i) { return(i/10) *16+(i % 10);} static int isValidBCD(uint8_t b) { return(b &0xf)< 10 &&(b > > 4)< 10;} static uint32_t MSF2LBA(uint8_t m, uint8_t s, uint8_t f) { return(m *60+s) *75+f;} static uint8_t readResponse(uint8_t response[16]) { uint8_t responseSize=0;while((CDROM_REG0 &0x20) &&(responseSize< 16)) { response[responseSize++]=CDROM_REG1;} return responseSize;} static uint8_t discardResponse() { uint8_t response[16];return readResponse(response);} static inline void initializeTime() { while(1) { uint32_t init=COUNTERS[1].value;uint32_t counter;while((counter=COUNTERS[1].value)==init);if(counter !=COUNTERS[1].value) continue;s_lastHSyncCounter=counter;break;} s_currentTime=0;} static inline uint32_t updateTime() { uint32_t lastHSyncCounter=s_lastHSyncCounter;uint32_t hsyncCounter;while(1) { hsyncCounter=COUNTERS[1].value;if(hsyncCounter !=COUNTERS[1].value) continue;break;} if(hsyncCounter< lastHSyncCounter) { hsyncCounter+=0x10000;} uint32_t currentTime=s_currentTime=s_currentTime+(hsyncCounter - lastHSyncCounter) *US_PER_HBLANK;s_lastHSyncCounter=hsyncCounter;return currentTime;} static inline uint32_t waitCDRomIRQ() { uint32_t time;do { time=updateTime();} while((IREG &IRQ_CDROM)==0);IREG &=~IRQ_CDROM;return time;} static inline int waitCDRomIRQWithTimeout(uint32_t *timeoutp) { uint32_t time=updateTime();uint32_t timeout= *timeoutp+time;do { time=updateTime();} while(((IREG &IRQ_CDROM)==0) &&(time<=timeout));int ret=(IREG &IRQ_CDROM) !=0; *timeoutp=time;IREG &=~IRQ_CDROM;return ret;} static inline uint8_t ackCDRomCause() { CDROM_REG0=1;uint8_t cause=CDROM_REG3_UC;if(cause &7) { CDROM_REG0=1;CDROM_REG3=7;} if(cause &0x18) { CDROM_REG0=1;CDROM_REG3=cause &0x18;} return cause &7;} int setMode(uint8_t mode) { uint8_t cause;CDROM_REG0=0;CDROM_REG2=mode;CDROM_REG1=CDL_SETMODE;waitCDRomIRQ();cause=ackCDRomCause();CDROM_REG1;if(cause !=3) return 0;return 1;} static inline int resetCDRom() { uint8_t cause;CDROM_REG0=1;CDROM_REG3=0x1f;CDROM_REG0=1;CDROM_REG2=0x1f;CDROM_REG0=0;CDROM_REG1=CDL_INIT;waitCDRomIRQ();cause=ackCDRomCause();CDROM_REG1;if(cause !=3) return 0;waitCDRomIRQ();cause=ackCDRomCause();CDROM_REG1;if(cause !=2) return 0;initializeTime();while(updateTime()< 10000);return setMode(0);} static int setLoc(uint8_t minute, uint8_t second, uint8_t frame) { uint8_t cause;CDROM_REG0=0;CDROM_REG2=minute;CDROM_REG2=second;CDROM_REG2=frame;CDROM_REG1=CDL_SETLOC;waitCDRomIRQ();cause=ackCDRomCause();CDROM_REG1;if(cause !=3) return 0;return 1;} static int seekPTo(uint8_t minute, uint8_t second, uint8_t frame) { uint8_t cause;CDROM_REG0=0;CDROM_REG2=minute;CDROM_REG2=second;CDROM_REG2=frame;CDROM_REG1=CDL_SETLOC;waitCDRomIRQ();cause=ackCDRomCause();CDROM_REG1;if(cause !=3) return 0;CDROM_REG0=0;CDROM_REG1=CDL_SEEKP;waitCDRomIRQ();cause=ackCDRomCause();CDROM_REG1;if(cause !=3) return 0;waitCDRomIRQ();cause=ackCDRomCause();CDROM_REG1;if(cause !=2) return 0;return 1;} static int seekLTo(uint8_t minute, uint8_t second, uint8_t frame) { uint8_t cause;CDROM_REG0=0;CDROM_REG2=minute;CDROM_REG2=second;CDROM_REG2=frame;CDROM_REG1=CDL_SETLOC;waitCDRomIRQ();cause=ackCDRomCause();CDROM_REG1;if(cause !=3) return 0;CDROM_REG0=0;CDROM_REG1=CDL_SEEKL;waitCDRomIRQ();cause=ackCDRomCause();CDROM_REG1;if(cause !=3) return 0;waitCDRomIRQ();cause=ackCDRomCause();CDROM_REG1;if(cause !=2) return 0;return 1;} uint8_t getCtrl() { uint8_t cause;CDROM_REG0=0;CDROM_REG1=CDL_NOP;waitCDRomIRQ();ackCDRomCause();uint8_t ctrl=CDROM_REG1;return ctrl;}) CESTER_BEFORE_ALL(cpu_tests
SPU_VOICES
#define SPU_VOICES
Definition spu.h:42
SPU_KEY_ON_LOW
#define SPU_KEY_ON_LOW
Definition spu.h:88
SPU_VOL_MAIN_LEFT
#define SPU_VOL_MAIN_LEFT
Definition spu.h:84
SPU_KEY_OFF_LOW
#define SPU_KEY_OFF_LOW
Definition spu.h:90
SPU_KEY_OFF_HIGH
#define SPU_KEY_OFF_HIGH
Definition spu.h:91
SPU_CTRL
#define SPU_CTRL
Definition spu.h:104
SPU_VOL_MAIN_RIGHT
#define SPU_VOL_MAIN_RIGHT
Definition spu.h:85
ramsyscall_printf
ramsyscall_printf("=== e01_kseg1_reads_no_fill ===\n")
i
int i
Definition gte-regio.c:297
spu_tests
spu_tests
Definition spu-adpcm-edge.c:189
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_HASH
Definition spu-adsr-edge.c:718
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_FIRST
Definition spu-adsr-edge.c:229
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_FIRST
Definition spu-adsr-edge.c:1117
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_MINMAX
Definition spu-adsr-edge.c:1159
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_HASH
Definition spu-adsr-edge.c:214
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_FIRST
Definition spu-adsr-edge.c:601
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_MINMAX
Definition spu-adsr-edge.c:487
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_MINMAX
Definition spu-adsr-edge.c:835
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_MINMAX
Definition spu-adsr-edge.c:139
SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_HASH
#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_HASH
Definition spu-adsr-edge.c:1402
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_HASH
Definition spu-adsr-edge.c:1294
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_MINMAX
Definition spu-adsr-edge.c:991
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_HASH
Definition spu-adsr-edge.c:694
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_HASH
Definition spu-adsr-edge.c:70
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_MINMAX
Definition spu-adsr-edge.c:115
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_LAST
Definition spu-adsr-edge.c:1108
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_LAST
Definition spu-adsr-edge.c:1000
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_FIRST
Definition spu-adsr-edge.c:301
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_HASH
Definition spu-adsr-edge.c:946
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_FIRST
Definition spu-adsr-edge.c:613
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_HASH
Definition spu-adsr-edge.c:262
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_LAST
Definition spu-adsr-edge.c:712
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_HASH
Definition spu-adsr-edge.c:1054
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_LAST
Definition spu-adsr-edge.c:184
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_HASH
Definition spu-adsr-edge.c:1330
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_HASH
Definition spu-adsr-edge.c:646
SPU_ADSR_EDGE_EXPECTED_DECAY_02_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_DECAY_02_MINMAX
Definition spu-adsr-edge.c:379
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_MINMAX
Definition spu-adsr-edge.c:1339
SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_LAST
#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_LAST
Definition spu-adsr-edge.c:1384
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_MINMAX
Definition spu-adsr-edge.c:223
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_MINMAX
Definition spu-adsr-edge.c:1147
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_MINMAX
Definition spu-adsr-edge.c:559
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_MINMAX
Definition spu-adsr-edge.c:739
SPU_ADSR_EDGE_EXPECTED_DECAY_00_LAST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_00_LAST
Definition spu-adsr-edge.c:352
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_LAST
Definition spu-adsr-edge.c:652
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_MINMAX
Definition spu-adsr-edge.c:1051
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_LAST
Definition spu-adsr-edge.c:40
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_FIRST
Definition spu-adsr-edge.c:733
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_MINMAX
Definition spu-adsr-edge.c:499
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_LAST
Definition spu-adsr-edge.c:676
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_MINMAX
Definition spu-adsr-edge.c:1267
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_LAST
Definition spu-adsr-edge.c:172
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_MINMAX
Definition spu-adsr-edge.c:823
SPU_ADSR_EDGE_EXPECTED_DECAY_0A_HASH
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0A_HASH
Definition spu-adsr-edge.c:406
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_LAST
Definition spu-adsr-edge.c:124
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_MINMAX
Definition spu-adsr-edge.c:847
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_FIRST
Definition spu-adsr-edge.c:757
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_FIRST
Definition spu-adsr-edge.c:1273
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_HASH
Definition spu-adsr-edge.c:910
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_MINMAX
Definition spu-adsr-edge.c:511
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_FIRST
Definition spu-adsr-edge.c:565
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_MINMAX
Definition spu-adsr-edge.c:163
SPU_ADSR_EDGE_EXPECTED_DECAY_02_FIRST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_02_FIRST
Definition spu-adsr-edge.c:373
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_MINMAX
Definition spu-adsr-edge.c:799
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_HASH
Definition spu-adsr-edge.c:1078
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_MINMAX
Definition spu-adsr-edge.c:1243
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_LAST
Definition spu-adsr-edge.c:220
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_HASH
Definition spu-adsr-edge.c:814
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_FIRST
Definition spu-adsr-edge.c:1105
SPU_ADSR_EDGE_EXPECTED_DECAY_0A_LAST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0A_LAST
Definition spu-adsr-edge.c:400
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_HASH
Definition spu-adsr-edge.c:634
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_MINMAX
Definition spu-adsr-edge.c:235
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_MINMAX
Definition spu-adsr-edge.c:475
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_FIRST
Definition spu-adsr-edge.c:661
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_MINMAX
Definition spu-adsr-edge.c:1123
SPU_ADSR_EDGE_EXPECTED_DECAY_02_HASH
#define SPU_ADSR_EDGE_EXPECTED_DECAY_02_HASH
Definition spu-adsr-edge.c:382
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_LAST
Definition spu-adsr-edge.c:556
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_LAST
Definition spu-adsr-edge.c:1276
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_LAST
Definition spu-adsr-edge.c:64
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_LAST
Definition spu-adsr-edge.c:136
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_LAST
Definition spu-adsr-edge.c:244
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_MINMAX
Definition spu-adsr-edge.c:595
SPU_ADSR_EDGE_RUN
#define SPU_ADSR_EDGE_RUN(name, adsr, mode, samples, keyoff, first, last, minmax, hash)
Definition spu-adsr-edge.c:1422
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_HASH
Definition spu-adsr-edge.c:238
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_MINMAX
Definition spu-adsr-edge.c:1315
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_LAST
Definition spu-adsr-edge.c:52
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_HASH
Definition spu-adsr-edge.c:622
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_MINMAX
Definition spu-adsr-edge.c:43
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_FIRST
Definition spu-adsr-edge.c:49
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_MINMAX
Definition spu-adsr-edge.c:1303
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_LAST
Definition spu-adsr-edge.c:1252
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_LAST
Definition spu-adsr-edge.c:928
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_LAST
Definition spu-adsr-edge.c:160
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_MINMAX
Definition spu-adsr-edge.c:931
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_HASH
Definition spu-adsr-edge.c:142
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_MINMAX
Definition spu-adsr-edge.c:283
SPU_ADSR_EDGE_EXPECTED_DECAY_0F_FIRST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0F_FIRST
Definition spu-adsr-edge.c:433
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_LAST
Definition spu-adsr-edge.c:1336
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_FIRST
Definition spu-adsr-edge.c:1021
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_HASH
Definition spu-adsr-edge.c:922
SPU_ADSR_EDGE_EXPECTED_DECAY_08_LAST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_08_LAST
Definition spu-adsr-edge.c:388
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_MINMAX
Definition spu-adsr-edge.c:1087
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_FIRST
Definition spu-adsr-edge.c:1009
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_FIRST
Definition spu-adsr-edge.c:1309
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_HASH
Definition spu-adsr-edge.c:790
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_LAST
Definition spu-adsr-edge.c:1288
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_LAST
Definition spu-adsr-edge.c:1132
SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_FIRST
#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_FIRST
Definition spu-adsr-edge.c:1393
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_FIRST
Definition spu-adsr-edge.c:265
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_FIRST
Definition spu-adsr-edge.c:121
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_FIRST
Definition spu-adsr-edge.c:313
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_HASH
Definition spu-adsr-edge.c:766
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_HASH
Definition spu-adsr-edge.c:526
SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_LAST
#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_LAST
Definition spu-adsr-edge.c:1396
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_HASH
Definition spu-adsr-edge.c:154
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_HASH
Definition spu-adsr-edge.c:886
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_MINMAX
Definition spu-adsr-edge.c:667
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_FIRST
Definition spu-adsr-edge.c:181
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_LAST
Definition spu-adsr-edge.c:76
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_FIRST
Definition spu-adsr-edge.c:1129
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_FIRST
Definition spu-adsr-edge.c:457
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_FIRST
Definition spu-adsr-edge.c:277
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_HASH
Definition spu-adsr-edge.c:1306
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_FIRST
Definition spu-adsr-edge.c:445
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_LAST
Definition spu-adsr-edge.c:268
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_FIRST
Definition spu-adsr-edge.c:1069
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_FIRST
Definition spu-adsr-edge.c:685
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_HASH
Definition spu-adsr-edge.c:598
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_LAST
Definition spu-adsr-edge.c:844
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_LAST
Definition spu-adsr-edge.c:1048
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_FIRST
Definition spu-adsr-edge.c:241
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_LAST
Definition spu-adsr-edge.c:88
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_MINMAX
Definition spu-adsr-edge.c:919
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_HASH
Definition spu-adsr-edge.c:874
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_FIRST
Definition spu-adsr-edge.c:85
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_LAST
Definition spu-adsr-edge.c:664
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_FIRST
Definition spu-adsr-edge.c:505
RELEASE_RATE
#define RELEASE_RATE(rate, exp)
Definition spu-adsr-edge.c:1421
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_FIRST
Definition spu-adsr-edge.c:169
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_MINMAX
Definition spu-adsr-edge.c:463
SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_FIRST
#define SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_FIRST
Definition spu-adsr-edge.c:1357
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_LAST
Definition spu-adsr-edge.c:292
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_LAST
Definition spu-adsr-edge.c:832
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_MINMAX
Definition spu-adsr-edge.c:1231
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_HASH
Definition spu-adsr-edge.c:274
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_HASH
Definition spu-adsr-edge.c:1210
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_HASH
Definition spu-adsr-edge.c:574
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_FIRST
Definition spu-adsr-edge.c:865
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_HASH
Definition spu-adsr-edge.c:658
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_HASH
Definition spu-adsr-edge.c:778
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_MINMAX
Definition spu-adsr-edge.c:607
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_HASH
Definition spu-adsr-edge.c:862
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_MINMAX
Definition spu-adsr-edge.c:247
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_HASH
Definition spu-adsr-edge.c:1342
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_FIRST
Definition spu-adsr-edge.c:1321
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_MINMAX
Definition spu-adsr-edge.c:655
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_FIRST
Definition spu-adsr-edge.c:973
SPU_ADSR_EDGE_EXPECTED_DECAY_0C_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0C_MINMAX
Definition spu-adsr-edge.c:415
SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_FIRST
#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_FIRST
Definition spu-adsr-edge.c:1369
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_LAST
Definition spu-adsr-edge.c:1180
SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_FIRST
#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_FIRST
Definition spu-adsr-edge.c:1405
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_HASH
Definition spu-adsr-edge.c:1246
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_HASH
Definition spu-adsr-edge.c:538
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_FIRST
Definition spu-adsr-edge.c:1237
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_FIRST
Definition spu-adsr-edge.c:289
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_LAST
Definition spu-adsr-edge.c:448
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_LAST
Definition spu-adsr-edge.c:964
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_FIRST
Definition spu-adsr-edge.c:1153
SPU_ADSR_EDGE_EXPECTED_DECAY_0C_HASH
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0C_HASH
Definition spu-adsr-edge.c:418
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_MINMAX
Definition spu-adsr-edge.c:871
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_LAST
Definition spu-adsr-edge.c:496
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_MINMAX
Definition spu-adsr-edge.c:967
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_LAST
Definition spu-adsr-edge.c:304
ATTACK_RATE
#define ATTACK_RATE(rate, exp)
Definition spu-adsr-edge.c:1419
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_MINMAX
Definition spu-adsr-edge.c:127
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_MINMAX
Definition spu-adsr-edge.c:307
SPU_ADSR_EDGE_EXPECTED_DECAY_00_FIRST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_00_FIRST
Definition spu-adsr-edge.c:349
SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_LAST
#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_LAST
Definition spu-adsr-edge.c:1372
SPU_ADSR_EDGE_EXPECTED_DECAY_0F_HASH
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0F_HASH
Definition spu-adsr-edge.c:442
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_LAST
Definition spu-adsr-edge.c:280
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_FIRST
Definition spu-adsr-edge.c:589
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_FIRST
Definition spu-adsr-edge.c:1165
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_HASH
Definition spu-adsr-edge.c:1174
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_LAST
Definition spu-adsr-edge.c:856
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_MINMAX
Definition spu-adsr-edge.c:523
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_HASH
Definition spu-adsr-edge.c:202
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_MINMAX
Definition spu-adsr-edge.c:547
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_LAST
Definition spu-adsr-edge.c:340
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_HASH
Definition spu-adsr-edge.c:826
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_FIRST
Definition spu-adsr-edge.c:877
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_HASH
Definition spu-adsr-edge.c:1282
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_HASH
Definition spu-adsr-edge.c:1318
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_FIRST
Definition spu-adsr-edge.c:1177
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_LAST
Definition spu-adsr-edge.c:688
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_MINMAX
Definition spu-adsr-edge.c:535
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_HASH
Definition spu-adsr-edge.c:562
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_LAST
Definition spu-adsr-edge.c:100
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_LAST
Definition spu-adsr-edge.c:328
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_FIRST
Definition spu-adsr-edge.c:481
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_MINMAX
Definition spu-adsr-edge.c:1207
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_FIRST
Definition spu-adsr-edge.c:133
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_HASH
Definition spu-adsr-edge.c:1138
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_FIRST
Definition spu-adsr-edge.c:625
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_LAST
Definition spu-adsr-edge.c:1024
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_HASH
Definition spu-adsr-edge.c:730
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_MINMAX
Definition spu-adsr-edge.c:67
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_LAST
Definition spu-adsr-edge.c:640
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_MINMAX
Definition spu-adsr-edge.c:691
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_MINMAX
Definition spu-adsr-edge.c:751
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_MINMAX
Definition spu-adsr-edge.c:1111
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_FIRST
Definition spu-adsr-edge.c:889
SPU_ADSR_EDGE_EXPECTED_DECAY_0E_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0E_MINMAX
Definition spu-adsr-edge.c:427
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_FIRST
Definition spu-adsr-edge.c:925
SPU_ADSR_EDGE_EXPECTED_DECAY_0E_FIRST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0E_FIRST
Definition spu-adsr-edge.c:421
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_MINMAX
Definition spu-adsr-edge.c:1351
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_MINMAX
Definition spu-adsr-edge.c:343
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_LAST
Definition spu-adsr-edge.c:988
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_HASH
Definition spu-adsr-edge.c:838
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_HASH
Definition spu-adsr-edge.c:1234
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_FIRST
Definition spu-adsr-edge.c:157
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_HASH
Definition spu-adsr-edge.c:1066
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_HASH
Definition spu-adsr-edge.c:310
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_LAST
Definition spu-adsr-edge.c:748
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_LAST
Definition spu-adsr-edge.c:1084
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_LAST
Definition spu-adsr-edge.c:520
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_FIRST
Definition spu-adsr-edge.c:1081
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_LAST
Definition spu-adsr-edge.c:196
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_MINMAX
Definition spu-adsr-edge.c:259
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_FIRST
Definition spu-adsr-edge.c:961
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_LAST
Definition spu-adsr-edge.c:1072
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_LAST
Definition spu-adsr-edge.c:1144
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_MINMAX
Definition spu-adsr-edge.c:943
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_LAST
Definition spu-adsr-edge.c:724
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_FIRST
Definition spu-adsr-edge.c:1057
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_FIRST
Definition spu-adsr-edge.c:985
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_FIRST
Definition spu-adsr-edge.c:817
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_HASH
Definition spu-adsr-edge.c:118
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_MINMAX
Definition spu-adsr-edge.c:1255
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_MINMAX
Definition spu-adsr-edge.c:1195
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_MINMAX
Definition spu-adsr-edge.c:331
SPU_ADSR_EDGE_EXPECTED_DECAY_0C_LAST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0C_LAST
Definition spu-adsr-edge.c:412
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_HASH
Definition spu-adsr-edge.c:1162
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_LAST
Definition spu-adsr-edge.c:232
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_HASH
Definition spu-adsr-edge.c:1090
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_FIRST
Definition spu-adsr-edge.c:577
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_MINMAX
Definition spu-adsr-edge.c:1015
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_HASH
Definition spu-adsr-edge.c:1186
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_HASH
Definition spu-adsr-edge.c:1018
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_FIRST
Definition spu-adsr-edge.c:1045
SPU_ADSR_EDGE_EXPECTED_DECAY_0F_LAST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0F_LAST
Definition spu-adsr-edge.c:436
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_HASH
Definition spu-adsr-edge.c:1126
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_LAST
Definition spu-adsr-edge.c:1096
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_FIRST
Definition spu-adsr-edge.c:1333
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_MINMAX
Definition spu-adsr-edge.c:679
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_FIRST
Definition spu-adsr-edge.c:205
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_FIRST
Definition spu-adsr-edge.c:1285
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_FIRST
Definition spu-adsr-edge.c:1345
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_FIRST
Definition spu-adsr-edge.c:541
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_MINMAX
Definition spu-adsr-edge.c:787
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_MINMAX
Definition spu-adsr-edge.c:295
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_LAST
Definition spu-adsr-edge.c:1192
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_FIRST
Definition spu-adsr-edge.c:649
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_MINMAX
Definition spu-adsr-edge.c:811
SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_HASH
#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_HASH
Definition spu-adsr-edge.c:1390
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_LAST
Definition spu-adsr-edge.c:700
SPU_ADSR_EDGE_EXPECTED_DECAY_01_HASH
#define SPU_ADSR_EDGE_EXPECTED_DECAY_01_HASH
Definition spu-adsr-edge.c:370
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_HASH
Definition spu-adsr-edge.c:802
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_HASH
Definition spu-adsr-edge.c:958
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_MINMAX
Definition spu-adsr-edge.c:175
SUSTAIN_RATE
#define SUSTAIN_RATE(rate, level, direction, exp)
Definition spu-adsr-edge.c:1420
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_FIRST
Definition spu-adsr-edge.c:745
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_FIRST
Definition spu-adsr-edge.c:1093
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_MINMAX
Definition spu-adsr-edge.c:727
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_MINMAX
Definition spu-adsr-edge.c:319
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_FIRST
Definition spu-adsr-edge.c:901
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_FIRST
Definition spu-adsr-edge.c:697
SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_HASH
#define SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_HASH
Definition spu-adsr-edge.c:1366
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_HASH
Definition spu-adsr-edge.c:334
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_FIRST
Definition spu-adsr-edge.c:109
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_LAST
Definition spu-adsr-edge.c:1228
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_FIRST
Definition spu-adsr-edge.c:937
SPU_ADSR_EDGE_EXPECTED_UNSET
#define SPU_ADSR_EDGE_EXPECTED_UNSET
Definition spu-adsr-edge.c:34
SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_MINMAX
Definition spu-adsr-edge.c:1411
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_MINMAX
Definition spu-adsr-edge.c:1099
SPU_ADSR_EDGE_EXPECTED_DECAY_0A_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0A_MINMAX
Definition spu-adsr-edge.c:403
SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_MINMAX
Definition spu-adsr-edge.c:1363
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_HASH
Definition spu-adsr-edge.c:478
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_LAST
Definition spu-adsr-edge.c:592
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_LAST
Definition spu-adsr-edge.c:460
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_HASH
Definition spu-adsr-edge.c:586
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_HASH
Definition spu-adsr-edge.c:898
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_LAST
Definition spu-adsr-edge.c:1120
SPU_ADSR_EDGE_EXPECTED_DECAY_01_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_DECAY_01_MINMAX
Definition spu-adsr-edge.c:367
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_MINMAX
Definition spu-adsr-edge.c:775
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_LAST
Definition spu-adsr-edge.c:1036
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_LAST
Definition spu-adsr-edge.c:616
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_HASH
Definition spu-adsr-edge.c:346
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_HASH
Definition spu-adsr-edge.c:94
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_MINMAX
Definition spu-adsr-edge.c:1075
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_HASH
Definition spu-adsr-edge.c:514
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_MINMAX
Definition spu-adsr-edge.c:907
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_MINMAX
Definition spu-adsr-edge.c:91
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_FIRST
Definition spu-adsr-edge.c:325
SPU_ADSR_EDGE_EXPECTED_DECAY_0C_FIRST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0C_FIRST
Definition spu-adsr-edge.c:409
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_MINMAX
Definition spu-adsr-edge.c:199
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_MINMAX
Definition spu-adsr-edge.c:55
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_FIRST
Definition spu-adsr-edge.c:253
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_HASH
Definition spu-adsr-edge.c:1102
SPU_ADSR_EDGE_EXPECTED_DECAY_02_LAST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_02_LAST
Definition spu-adsr-edge.c:376
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_MINMAX
Definition spu-adsr-edge.c:883
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_LAST
Definition spu-adsr-edge.c:1156
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_FIRST
Definition spu-adsr-edge.c:949
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_FIRST
Definition spu-adsr-edge.c:1213
SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_HASH
#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_HASH
Definition spu-adsr-edge.c:1378
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_FIRST
Definition spu-adsr-edge.c:1297
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_FIRST
Definition spu-adsr-edge.c:769
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_LAST
Definition spu-adsr-edge.c:916
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_FIRST
Definition spu-adsr-edge.c:61
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_HASH
Definition spu-adsr-edge.c:106
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_FIRST
Definition spu-adsr-edge.c:1201
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_MINMAX
Definition spu-adsr-edge.c:1219
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_FIRST
Definition spu-adsr-edge.c:913
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_FIRST
Definition spu-adsr-edge.c:145
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_HASH
Definition spu-adsr-edge.c:610
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_MINMAX
Definition spu-adsr-edge.c:1183
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_FIRST
Definition spu-adsr-edge.c:1189
SPU_ADSR_EDGE_EXPECTED_DECAY_08_HASH
#define SPU_ADSR_EDGE_EXPECTED_DECAY_08_HASH
Definition spu-adsr-edge.c:394
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_FIRST
Definition spu-adsr-edge.c:841
SPU_ADSR_EDGE_EXPECTED_DECAY_08_FIRST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_08_FIRST
Definition spu-adsr-edge.c:385
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_FIRST
Definition spu-adsr-edge.c:829
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_MINMAX
Definition spu-adsr-edge.c:1063
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_MINMAX
Definition spu-adsr-edge.c:703
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_MINMAX
Definition spu-adsr-edge.c:571
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_FIRST
Definition spu-adsr-edge.c:37
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_HASH
Definition spu-adsr-edge.c:754
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_HASH
Definition spu-adsr-edge.c:286
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_HASH
Definition spu-adsr-edge.c:1030
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_LAST
Definition spu-adsr-edge.c:316
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_HASH
Definition spu-adsr-edge.c:1270
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_HASH
Definition spu-adsr-edge.c:670
SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_LAST
#define SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_LAST
Definition spu-adsr-edge.c:1360
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_LAST
Definition spu-adsr-edge.c:1060
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_HASH
Definition spu-adsr-edge.c:1114
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_LAST
Definition spu-adsr-edge.c:1204
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_LAST
Definition spu-adsr-edge.c:880
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_HASH
Definition spu-adsr-edge.c:1006
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_LAST
Definition spu-adsr-edge.c:208
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_HASH
Definition spu-adsr-edge.c:466
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_FIRST
Definition spu-adsr-edge.c:493
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_HASH
Definition spu-adsr-edge.c:850
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_MINMAX
Definition spu-adsr-edge.c:583
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_MINMAX
Definition spu-adsr-edge.c:451
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_MINMAX
Definition spu-adsr-edge.c:643
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_HASH
Definition spu-adsr-edge.c:1198
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_LAST
Definition spu-adsr-edge.c:868
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_FIRST
Definition spu-adsr-edge.c:529
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_LAST
Definition spu-adsr-edge.c:784
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_FIRST
Definition spu-adsr-edge.c:853
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_HASH
Definition spu-adsr-edge.c:490
SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_MINMAX
Definition spu-adsr-edge.c:1387
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_MINMAX
Definition spu-adsr-edge.c:1291
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_HASH
Definition spu-adsr-edge.c:1222
SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_FIRST
#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_FIRST
Definition spu-adsr-edge.c:1381
SPU_ADSR_EDGE_EXPECTED_DECAY_00_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_DECAY_00_MINMAX
Definition spu-adsr-edge.c:355
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_LAST
Definition spu-adsr-edge.c:568
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_LAST
Definition spu-adsr-edge.c:736
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_HASH
Definition spu-adsr-edge.c:250
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_LAST
Definition spu-adsr-edge.c:484
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_MINMAX
Definition spu-adsr-edge.c:1027
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_LAST
Definition spu-adsr-edge.c:148
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_MINMAX
Definition spu-adsr-edge.c:631
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_HASH
Definition spu-adsr-edge.c:706
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_HASH
Definition spu-adsr-edge.c:502
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_FIRST
Definition spu-adsr-edge.c:73
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_FIRST
Definition spu-adsr-edge.c:709
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_LAST
Definition spu-adsr-edge.c:1012
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_MINMAX
Definition spu-adsr-edge.c:151
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_HASH
Definition spu-adsr-edge.c:58
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_FIRST
Definition spu-adsr-edge.c:517
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_MINMAX
Definition spu-adsr-edge.c:715
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_FIRST
Definition spu-adsr-edge.c:997
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_HASH
Definition spu-adsr-edge.c:1150
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_LAST
Definition spu-adsr-edge.c:1312
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_HASH
Definition spu-adsr-edge.c:298
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_HASH
Definition spu-adsr-edge.c:970
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_LAST
Definition spu-adsr-edge.c:820
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_LAST
Definition spu-adsr-edge.c:256
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_FIRST
Definition spu-adsr-edge.c:217
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_LAST
Definition spu-adsr-edge.c:580
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_LAST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_LAST
Definition spu-adsr-edge.c:112
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_HASH
Definition spu-adsr-edge.c:1354
SPU_ADSR_EDGE_EXPECTED_DECAY_0E_HASH
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0E_HASH
Definition spu-adsr-edge.c:430
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_MINMAX
Definition spu-adsr-edge.c:1135
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_HASH
Definition spu-adsr-edge.c:742
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_FIRST
Definition spu-adsr-edge.c:469
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_MINMAX
Definition spu-adsr-edge.c:211
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_HASH
Definition spu-adsr-edge.c:130
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_LAST
Definition spu-adsr-edge.c:796
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_MINMAX
Definition spu-adsr-edge.c:859
SPU_ADSR_EDGE_EXPECTED_DECAY_0A_FIRST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0A_FIRST
Definition spu-adsr-edge.c:397
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_MINMAX
Definition spu-adsr-edge.c:619
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_FIRST
Definition spu-adsr-edge.c:1225
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_MINMAX
Definition spu-adsr-edge.c:79
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_FIRST
Definition spu-adsr-edge.c:805
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_HASH
Definition spu-adsr-edge.c:190
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_LAST
Definition spu-adsr-edge.c:1216
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_FIRST
Definition spu-adsr-edge.c:781
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_LAST
Definition spu-adsr-edge.c:808
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_MINMAX
Definition spu-adsr-edge.c:187
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_FIRST
Definition spu-adsr-edge.c:337
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_MINMAX
Definition spu-adsr-edge.c:895
SPU_ADSR_EDGE_EXPECTED_DECAY_00_HASH
#define SPU_ADSR_EDGE_EXPECTED_DECAY_00_HASH
Definition spu-adsr-edge.c:358
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_HASH
Definition spu-adsr-edge.c:934
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_MINMAX
Definition spu-adsr-edge.c:763
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_MINMAX
Definition spu-adsr-edge.c:1003
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_MINMAX
Definition spu-adsr-edge.c:979
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_HASH
Definition spu-adsr-edge.c:682
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_LAST
Definition spu-adsr-edge.c:1264
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_HASH
Definition spu-adsr-edge.c:1042
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_MINMAX
Definition spu-adsr-edge.c:955
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_HASH
Definition spu-adsr-edge.c:994
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_LAST
Definition spu-adsr-edge.c:1168
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_HASH
Definition spu-adsr-edge.c:550
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_FIRST
Definition spu-adsr-edge.c:1141
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_FIRST
Definition spu-adsr-edge.c:721
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_FIRST
Definition spu-adsr-edge.c:1261
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_FIRST
Definition spu-adsr-edge.c:673
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_LAST
Definition spu-adsr-edge.c:544
SPU_ADSR_EDGE_EXPECTED_DECAY_08_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_DECAY_08_MINMAX
Definition spu-adsr-edge.c:391
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_FIRST
Definition spu-adsr-edge.c:193
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_LAST
Definition spu-adsr-edge.c:976
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_LAST
Definition spu-adsr-edge.c:532
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_LAST
Definition spu-adsr-edge.c:940
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_LAST
Definition spu-adsr-edge.c:604
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_LAST
Definition spu-adsr-edge.c:952
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_HASH
Definition spu-adsr-edge.c:82
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_LAST
Definition spu-adsr-edge.c:1240
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_LAST
Definition spu-adsr-edge.c:760
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_LAST
Definition spu-adsr-edge.c:628
SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_LAST
#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_LAST
Definition spu-adsr-edge.c:1408
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_FIRST
Definition spu-adsr-edge.c:1033
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_HASH
Definition spu-adsr-edge.c:454
SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_MINMAX
Definition spu-adsr-edge.c:1399
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_LAST
Definition spu-adsr-edge.c:772
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_HASH
Definition spu-adsr-edge.c:322
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_FIRST
Definition spu-adsr-edge.c:637
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_MINMAX
Definition spu-adsr-edge.c:271
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_MINMAX
Definition spu-adsr-edge.c:1279
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_LAST
Definition spu-adsr-edge.c:1348
SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_MINMAX
Definition spu-adsr-edge.c:1375
SPU_ADSR_EDGE_EXPECTED_DECAY_0F_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0F_MINMAX
Definition spu-adsr-edge.c:439
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_LAST
Definition spu-adsr-edge.c:904
SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_HASH
Definition spu-adsr-edge.c:226
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_MINMAX
Definition spu-adsr-edge.c:1327
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_HASH
Definition spu-adsr-edge.c:166
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_MINMAX
Definition spu-adsr-edge.c:103
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_FIRST
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_FIRST
Definition spu-adsr-edge.c:97
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_MINMAX
Definition spu-adsr-edge.c:1171
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_FIRST
Definition spu-adsr-edge.c:793
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_LAST
Definition spu-adsr-edge.c:1300
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_LAST
Definition spu-adsr-edge.c:472
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_FIRST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_FIRST
Definition spu-adsr-edge.c:553
SPU_ADSR_EDGE_EXPECTED_DECAY_01_FIRST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_01_FIRST
Definition spu-adsr-edge.c:361
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_LAST
Definition spu-adsr-edge.c:892
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_HASH
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_HASH
Definition spu-adsr-edge.c:1258
SPU_ADSR_EDGE_EXPECTED_DECAY_0E_LAST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_0E_LAST
Definition spu-adsr-edge.c:424
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_LAST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_LAST
Definition spu-adsr-edge.c:1324
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_MINMAX
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_MINMAX
Definition spu-adsr-edge.c:1039
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_LAST
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_LAST
Definition spu-adsr-edge.c:508
SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_HASH
#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_HASH
Definition spu-adsr-edge.c:1414
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_HASH
Definition spu-adsr-edge.c:178
SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_FIRST
#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_FIRST
Definition spu-adsr-edge.c:1249
SPU_ADSR_EDGE_EXPECTED_DECAY_01_LAST
#define SPU_ADSR_EDGE_EXPECTED_DECAY_01_LAST
Definition spu-adsr-edge.c:364
SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_HASH
#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_HASH
Definition spu-adsr-edge.c:982
SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_HASH
#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_HASH
Definition spu-adsr-edge.c:46
DECAY
#define DECAY(shift)
Definition spu-adsrsus.c:39
SUSTAIN
#define SUSTAIN(step, shift, level, direction, exp)
Definition spu-adsrsus.c:40
SPU_UPLOAD_ADDR
#define SPU_UPLOAD_ADDR
Definition spu-capamp.c:31
muteSpu
muteSpu()
spu_reset_quiet
spu_reset_quiet()
mode
static void uint32_t mode
Definition syscalls.h:231
uint32_t
void uint32_t(classId, spec)
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