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Macros
#define	SPU_ADSR_EDGE_EXPECTED_UNSET 0xffffffffu

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_08_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_08_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_08_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_08_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0A_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0A_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0A_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0A_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0E_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0E_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0E_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0E_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_DECAY_0F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

#define	SPU_ADSR_EDGE_MACROS_DEFINED

#define	ATTACK_RATE(rate, exp) ATTACK((rate) & 3, ((rate) >> 2) & 31, exp)

#define	SUSTAIN_RATE(rate, level, direction, exp) SUSTAIN((rate) & 3, ((rate) >> 2) & 31, level, direction, exp)

#define	RELEASE_RATE(rate, exp) RELEASE(((rate) >> 2) & 31, exp)

#define	SPU_ADSR_EDGE_RUN(name, adsr, mode, samples, keyoff, first, last, minmax, hash) spu_adsr_edge_run_trace(name, adsr, mode, samples, keyoff, first, last, minmax, hash)

Macro Definition Documentation

◆ ATTACK_RATE

#define ATTACK_RATE	(	rate,
		exp
	)	ATTACK((rate) & 3, ((rate) >> 2) & 31, exp)

◆ RELEASE_RATE

#define RELEASE_RATE	(	rate,
		exp
	)	RELEASE(((rate) >> 2) & 31, exp)

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_04_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_24_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_28_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_EXP_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_04_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_24_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_28_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_FIRST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_HASH

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_LAST

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_ATTACK_LIN_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_FIRST

#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_HASH

#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_LAST

#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_ATTACK_PEAK_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_FIRST

#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_HASH

#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_LAST

#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_BOUNDARY_RELEASE_ZERO_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_00_FIRST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_00_HASH

#define SPU_ADSR_EDGE_EXPECTED_DECAY_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_00_LAST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_00_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_DECAY_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_01_FIRST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_01_HASH

#define SPU_ADSR_EDGE_EXPECTED_DECAY_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_01_LAST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_01_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_DECAY_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_02_FIRST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_02_HASH

#define SPU_ADSR_EDGE_EXPECTED_DECAY_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_02_LAST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_02_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_DECAY_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_08_FIRST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_08_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_08_HASH

#define SPU_ADSR_EDGE_EXPECTED_DECAY_08_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_08_LAST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_08_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_08_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_DECAY_08_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0A_FIRST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0A_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0A_HASH

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0A_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0A_LAST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0A_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0A_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0A_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0C_FIRST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0C_HASH

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0C_LAST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0C_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0E_FIRST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0E_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0E_HASH

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0E_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0E_LAST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0E_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0E_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0E_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0F_FIRST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0F_HASH

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0F_LAST

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_DECAY_0F_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_DECAY_0F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_FIRST

#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_HASH

#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_LAST

#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_7FFF_THEN_RELEASE_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_FIRST

#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_HASH

#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_LAST

#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_MANUAL_ENVX_ZERO_THEN_ATTACK_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_EXP_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_FIRST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_HASH

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_LAST

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_RELEASE_FROM_SUSTAIN_LIN_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_EXP_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_DOWN_LIN_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_04_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_05_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_06_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_07_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_08_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_09_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0A_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0B_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0D_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0E_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_LEVEL_0F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_EXP_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_00_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_01_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_02_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_03_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_2C_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_30_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_34_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_40_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_60_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_FIRST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_HASH

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_LAST

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_SUSTAIN_UP_LIN_7F_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_FIRST

#define SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_FIRST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_HASH

#define SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_HASH SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_LAST

#define SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_LAST SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_MINMAX

#define SPU_ADSR_EDGE_EXPECTED_TIMING_KEYON_ZERO_START_MINMAX SPU_ADSR_EDGE_EXPECTED_UNSET

◆ SPU_ADSR_EDGE_EXPECTED_UNSET

#define SPU_ADSR_EDGE_EXPECTED_UNSET 0xffffffffu

◆ SPU_ADSR_EDGE_MACROS_DEFINED

#define SPU_ADSR_EDGE_MACROS_DEFINED

◆ SPU_ADSR_EDGE_RUN

#define SPU_ADSR_EDGE_RUN	(	name,
		adsr,
		mode,
		samples,
		keyoff,
		first,
		last,
		minmax,
		hash
	)	spu_adsr_edge_run_trace(name, adsr, mode, samples, keyoff, first, last, minmax, hash)

◆ SUSTAIN_RATE

#define SUSTAIN_RATE	(	rate,
		level,
		direction,
		exp
	)	SUSTAIN((rate) & 3, ((rate) >> 2) & 31, level, direction, exp)

Macros