36static void drawT_NEG_U_K05(
void) {
38 rasterClearTestRegion(0, 0, 24, 16);
40 setTextureWindow(0, 0, 0, 0);
46 rasterFlushPrimitive();
52static void drawT_NEG_V_K05(
void) {
54 rasterClearTestRegion(0, 0, 24, 16);
56 setTextureWindow(0, 0, 0, 0);
62 rasterFlushPrimitive();
68static void drawT_NEG_BOTH_K05(
void) {
70 rasterClearTestRegion(0, 0, 24, 16);
72 setTextureWindow(0, 0, 0, 0);
78 rasterFlushPrimitive();
84static void drawT_NEG_U_K16(
void) {
86 rasterClearTestRegion(0, 0, 24, 16);
88 setTextureWindow(0, 0, 0, 0);
94 rasterFlushPrimitive();
101static void drawT_CROSS_45_K05(
void) {
103 rasterClearTestRegion(0, 0, 24, 16);
105 setTextureWindow(0, 0, 0, 0);
111 rasterFlushPrimitive();
118static void drawT_CROSS_90_K16(
void) {
120 rasterClearTestRegion(0, 0, 24, 16);
122 setTextureWindow(0, 0, 0, 0);
128 rasterFlushPrimitive();
137CESTER_TEST(ar_neg_u_k05_vertex, gpu_raster_phase19,
142CESTER_TEST(ar_neg_u_k05_top_near, gpu_raster_phase19,
147CESTER_TEST(ar_neg_u_k05_left_near, gpu_raster_phase19,
152CESTER_TEST(ar_neg_u_k05_interior, gpu_raster_phase19,
157CESTER_TEST(ar_neg_u_k05_top_far, gpu_raster_phase19,
166CESTER_TEST(ar_neg_v_k05_vertex, gpu_raster_phase19,
171CESTER_TEST(ar_neg_v_k05_top_near, gpu_raster_phase19,
176CESTER_TEST(ar_neg_v_k05_left_near, gpu_raster_phase19,
181CESTER_TEST(ar_neg_v_k05_interior, gpu_raster_phase19,
186CESTER_TEST(ar_neg_v_k05_top_far, gpu_raster_phase19,
195CESTER_TEST(ar_neg_both_k05_vertex, gpu_raster_phase19,
196 drawT_NEG_BOTH_K05();
200CESTER_TEST(ar_neg_both_k05_top_near, gpu_raster_phase19,
201 drawT_NEG_BOTH_K05();
205CESTER_TEST(ar_neg_both_k05_left_near, gpu_raster_phase19,
206 drawT_NEG_BOTH_K05();
210CESTER_TEST(ar_neg_both_k05_interior, gpu_raster_phase19,
211 drawT_NEG_BOTH_K05();
215CESTER_TEST(ar_neg_both_k05_top_far, gpu_raster_phase19,
216 drawT_NEG_BOTH_K05();
224CESTER_TEST(ar_neg_u_k16_vertex, gpu_raster_phase19,
229CESTER_TEST(ar_neg_u_k16_top_near, gpu_raster_phase19,
234CESTER_TEST(ar_neg_u_k16_left_near, gpu_raster_phase19,
239CESTER_TEST(ar_neg_u_k16_interior, gpu_raster_phase19,
244CESTER_TEST(ar_neg_u_k16_top_far, gpu_raster_phase19,
253CESTER_TEST(ar_cross_45_k05_vertex, gpu_raster_phase19,
254 drawT_CROSS_45_K05();
258CESTER_TEST(ar_cross_45_k05_top_near, gpu_raster_phase19,
259 drawT_CROSS_45_K05();
263CESTER_TEST(ar_cross_45_k05_left_near, gpu_raster_phase19,
264 drawT_CROSS_45_K05();
268CESTER_TEST(ar_cross_45_k05_interior, gpu_raster_phase19,
269 drawT_CROSS_45_K05();
273CESTER_TEST(ar_cross_45_k05_top_far, gpu_raster_phase19,
274 drawT_CROSS_45_K05();
282CESTER_TEST(ar_cross_90_k16_vertex, gpu_raster_phase19,
283 drawT_CROSS_90_K16();
287CESTER_TEST(ar_cross_90_k16_top_near, gpu_raster_phase19,
288 drawT_CROSS_90_K16();
292CESTER_TEST(ar_cross_90_k16_left_near, gpu_raster_phase19,
293 drawT_CROSS_90_K16();
297CESTER_TEST(ar_cross_90_k16_interior, gpu_raster_phase19,
298 drawT_CROSS_90_K16();
302CESTER_TEST(ar_cross_90_k16_top_far, gpu_raster_phase19,
303 drawT_CROSS_90_K16();
CESTER_BODY(static int s_got40;static int s_got80;static uint32_t s_cause;static uint32_t s_epc;static uint32_t s_from;static uint32_t *s_resume;static uint32_t *s_regs;static uint32_t(*s_customhandler)()=NULL;static uint32_t s_oldIMASK;static uint32_t s_oldDPCR;static uint32_t s_oldDICR;uint32_t handler(uint32_t *regs, uint32_t from) { if(from==0x40) s_got40=1;if(from==0x80) s_got80=1;uint32_t cause;uint32_t epc;s_from=from;asm("mfc0 %0, $13\nnop\nmfc0 %1, $14\nnop" :"=r"(cause), "=r"(epc));s_cause=cause;s_epc=epc;if(s_customhandler) { return s_customhandler();} else { return s_resume ?((uint32_t) s_resume) :(epc+4);} } void installExceptionHandlers(uint32_t(*handler)(uint32_t *regs, uint32_t from));void uninstallExceptionHandlers();uint32_t branchbranch1();uint32_t branchbranch2();uint32_t jumpjump1();uint32_t jumpjump2();uint32_t cpu_LWR_LWL_half(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_nodelay(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_delayed(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_load_different(uint32_t buff[], uint32_t initial);uint32_t cpu_LW_LWR(uint32_t buff[], uint32_t initial);uint32_t cpu_delayed_load(uint32_t buff[], uint32_t override);uint32_t cpu_delayed_load_cancelled(uint32_t buff[], uint32_t override);uint64_t cpu_delayed_load_load(uint32_t buff[], uint32_t override);uint32_t linkandload();uint32_t lwandlink();uint32_t nolink();static int s_interruptsWereEnabled;) CESTER_BEFORE_EACH(cpu_tests
CESTER_TEST(cpu_cop0_basic_write_bp, cpu_tests, uint32_t expectedEPC;uint32_t t;volatile uint32_t *ptr=(volatile uint32_t *) 0x58; *ptr=1;__asm__ volatile("" " lui %0, 0b1100101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0xfffffff0\n" " mtc0 %0, $9\n" :"=r"(t));cester_assert_uint_eq(1, *ptr);__asm__ volatile("la %0, 1f\n1:\nsw $0, 0x58($0)" :"=r"(expectedEPC));__asm__ volatile("mtc0 $0, $7\n");cester_assert_uint_eq(0, *ptr);cester_assert_uint_eq(1, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0x40, s_from);cester_assert_uint_eq(expectedEPC, s_epc);) CESTER_TEST(cpu_cop0_kseg_write_bp
#define EXPECT_NEG_U_K05_INTERIOR
Definition raster-expected-phase19.h:83
#define EXPECT_CROSS_90_K16_TOP_NEAR
Definition raster-expected-phase19.h:161
#define EXPECT_NEG_U_K05_LEFT_NEAR
Definition raster-expected-phase19.h:82
#define EXPECT_NEG_U_K05_TOP_FAR
Definition raster-expected-phase19.h:84
#define EXPECT_CROSS_45_K05_INTERIOR
Definition raster-expected-phase19.h:147
#define EXPECT_NEG_U_K16_TOP_FAR
Definition raster-expected-phase19.h:132
#define EXPECT_NEG_V_K05_TOP_NEAR
Definition raster-expected-phase19.h:97
#define EXPECT_NEG_U_K16_TOP_NEAR
Definition raster-expected-phase19.h:129
#define EXPECT_NEG_U_K05_VERTEX
Definition raster-expected-phase19.h:80
#define EXPECT_NEG_V_K05_INTERIOR
Definition raster-expected-phase19.h:99
#define EXPECT_NEG_BOTH_K05_INTERIOR
Definition raster-expected-phase19.h:115
#define EXPECT_NEG_BOTH_K05_LEFT_NEAR
Definition raster-expected-phase19.h:114
#define EXPECT_CROSS_90_K16_INTERIOR
Definition raster-expected-phase19.h:163
#define EXPECT_CROSS_90_K16_VERTEX
Definition raster-expected-phase19.h:160
#define EXPECT_NEG_V_K05_TOP_FAR
Definition raster-expected-phase19.h:100
#define EXPECT_NEG_V_K05_VERTEX
Definition raster-expected-phase19.h:96
#define EXPECT_NEG_BOTH_K05_TOP_NEAR
Definition raster-expected-phase19.h:113
#define EXPECT_CROSS_90_K16_TOP_FAR
Definition raster-expected-phase19.h:164
#define EXPECT_NEG_U_K16_INTERIOR
Definition raster-expected-phase19.h:131
#define EXPECT_NEG_U_K16_LEFT_NEAR
Definition raster-expected-phase19.h:130
#define EXPECT_NEG_V_K05_LEFT_NEAR
Definition raster-expected-phase19.h:98
#define EXPECT_CROSS_45_K05_TOP_NEAR
Definition raster-expected-phase19.h:145
#define EXPECT_NEG_U_K05_TOP_NEAR
Definition raster-expected-phase19.h:81
#define EXPECT_NEG_U_K16_VERTEX
Definition raster-expected-phase19.h:128
#define EXPECT_CROSS_45_K05_VERTEX
Definition raster-expected-phase19.h:144
#define EXPECT_CROSS_90_K16_LEFT_NEAR
Definition raster-expected-phase19.h:162
#define EXPECT_NEG_BOTH_K05_TOP_FAR
Definition raster-expected-phase19.h:116
#define EXPECT_NEG_BOTH_K05_VERTEX
Definition raster-expected-phase19.h:112
#define EXPECT_CROSS_45_K05_TOP_FAR
Definition raster-expected-phase19.h:148
#define EXPECT_CROSS_45_K05_LEFT_NEAR
Definition raster-expected-phase19.h:146
#define TEX17_TY
Definition texture-fixture-phase17.h:58
#define TEX17_TPAGE
Definition texture-fixture-phase17.h:65
#define TEX17_TX
Definition texture-fixture-phase17.h:57
#define PHASE17_ASSERT_PIXEL_EQ(expected, x_, y_)
Definition texture-fixture-phase17.h:102
#define TEX17_CLUT_FIELD
Definition texture-fixture-phase17.h:66
#define TEX_MOD_NEUTRAL
Definition texture-fixtures.h:328