40static void drawT_AXIS_K01(
void) {
42 rasterClearTestRegion(0, 0, 24, 16);
44 setTextureWindow(0, 0, 0, 0);
50 rasterFlushPrimitive();
54static void drawT_AXIS_K02(
void) {
56 rasterClearTestRegion(0, 0, 24, 16);
58 setTextureWindow(0, 0, 0, 0);
64 rasterFlushPrimitive();
68static void drawT_AXIS_K03(
void) {
70 rasterClearTestRegion(0, 0, 24, 16);
72 setTextureWindow(0, 0, 0, 0);
78 rasterFlushPrimitive();
82static void drawT_AXIS_K05(
void) {
84 rasterClearTestRegion(0, 0, 24, 16);
86 setTextureWindow(0, 0, 0, 0);
92 rasterFlushPrimitive();
96static void drawT_AXIS_K08(
void) {
98 rasterClearTestRegion(0, 0, 24, 16);
100 setTextureWindow(0, 0, 0, 0);
106 rasterFlushPrimitive();
110static void drawT_AXIS_K16(
void) {
112 rasterClearTestRegion(0, 0, 24, 16);
114 setTextureWindow(0, 0, 0, 0);
120 rasterFlushPrimitive();
134CESTER_TEST(ar_axis_k01_top_near, gpu_raster_phase18,
139CESTER_TEST(ar_axis_k01_left_near, gpu_raster_phase18,
144CESTER_TEST(ar_axis_k01_interior, gpu_raster_phase18,
149CESTER_TEST(ar_axis_k01_top_far, gpu_raster_phase18,
163CESTER_TEST(ar_axis_k02_top_near, gpu_raster_phase18,
168CESTER_TEST(ar_axis_k02_left_near, gpu_raster_phase18,
173CESTER_TEST(ar_axis_k02_interior, gpu_raster_phase18,
178CESTER_TEST(ar_axis_k02_top_far, gpu_raster_phase18,
192CESTER_TEST(ar_axis_k03_top_near, gpu_raster_phase18,
197CESTER_TEST(ar_axis_k03_left_near, gpu_raster_phase18,
202CESTER_TEST(ar_axis_k03_interior, gpu_raster_phase18,
207CESTER_TEST(ar_axis_k03_top_far, gpu_raster_phase18,
221CESTER_TEST(ar_axis_k05_top_near, gpu_raster_phase18,
226CESTER_TEST(ar_axis_k05_left_near, gpu_raster_phase18,
231CESTER_TEST(ar_axis_k05_interior, gpu_raster_phase18,
236CESTER_TEST(ar_axis_k05_top_far, gpu_raster_phase18,
250CESTER_TEST(ar_axis_k08_top_near, gpu_raster_phase18,
255CESTER_TEST(ar_axis_k08_left_near, gpu_raster_phase18,
260CESTER_TEST(ar_axis_k08_interior, gpu_raster_phase18,
265CESTER_TEST(ar_axis_k08_top_far, gpu_raster_phase18,
279CESTER_TEST(ar_axis_k16_top_near, gpu_raster_phase18,
284CESTER_TEST(ar_axis_k16_left_near, gpu_raster_phase18,
289CESTER_TEST(ar_axis_k16_interior, gpu_raster_phase18,
294CESTER_TEST(ar_axis_k16_top_far, gpu_raster_phase18,
CESTER_BODY(static int s_got40;static int s_got80;static uint32_t s_cause;static uint32_t s_epc;static uint32_t s_from;static uint32_t *s_resume;static uint32_t *s_regs;static uint32_t(*s_customhandler)()=NULL;static uint32_t s_oldIMASK;static uint32_t s_oldDPCR;static uint32_t s_oldDICR;uint32_t handler(uint32_t *regs, uint32_t from) { if(from==0x40) s_got40=1;if(from==0x80) s_got80=1;uint32_t cause;uint32_t epc;s_from=from;asm("mfc0 %0, $13\nnop\nmfc0 %1, $14\nnop" :"=r"(cause), "=r"(epc));s_cause=cause;s_epc=epc;if(s_customhandler) { return s_customhandler();} else { return s_resume ?((uint32_t) s_resume) :(epc+4);} } void installExceptionHandlers(uint32_t(*handler)(uint32_t *regs, uint32_t from));void uninstallExceptionHandlers();uint32_t branchbranch1();uint32_t branchbranch2();uint32_t jumpjump1();uint32_t jumpjump2();uint32_t cpu_LWR_LWL_half(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_nodelay(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_delayed(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_load_different(uint32_t buff[], uint32_t initial);uint32_t cpu_LW_LWR(uint32_t buff[], uint32_t initial);uint32_t cpu_delayed_load(uint32_t buff[], uint32_t override);uint32_t cpu_delayed_load_cancelled(uint32_t buff[], uint32_t override);uint64_t cpu_delayed_load_load(uint32_t buff[], uint32_t override);uint32_t linkandload();uint32_t lwandlink();uint32_t nolink();static int s_interruptsWereEnabled;) CESTER_BEFORE_EACH(cpu_tests
CESTER_TEST(cpu_cop0_basic_write_bp, cpu_tests, uint32_t expectedEPC;uint32_t t;volatile uint32_t *ptr=(volatile uint32_t *) 0x58; *ptr=1;__asm__ volatile("" " lui %0, 0b1100101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0xfffffff0\n" " mtc0 %0, $9\n" :"=r"(t));cester_assert_uint_eq(1, *ptr);__asm__ volatile("la %0, 1f\n1:\nsw $0, 0x58($0)" :"=r"(expectedEPC));__asm__ volatile("mtc0 $0, $7\n");cester_assert_uint_eq(0, *ptr);cester_assert_uint_eq(1, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0x40, s_from);cester_assert_uint_eq(expectedEPC, s_epc);) CESTER_TEST(cpu_cop0_kseg_write_bp
#define EXPECT_K01_LEFT_NEAR
Definition raster-expected-phase18.h:87
#define EXPECT_K05_VERTEX
Definition raster-expected-phase18.h:130
#define EXPECT_K05_TOP_NEAR
Definition raster-expected-phase18.h:131
#define EXPECT_K16_LEFT_NEAR
Definition raster-expected-phase18.h:162
#define EXPECT_K08_TOP_NEAR
Definition raster-expected-phase18.h:146
#define EXPECT_K01_TOP_NEAR
Definition raster-expected-phase18.h:86
#define EXPECT_K08_LEFT_NEAR
Definition raster-expected-phase18.h:147
#define EXPECT_K16_INTERIOR
Definition raster-expected-phase18.h:163
#define EXPECT_K03_INTERIOR
Definition raster-expected-phase18.h:118
#define EXPECT_K03_LEFT_NEAR
Definition raster-expected-phase18.h:117
#define EXPECT_K16_VERTEX
Definition raster-expected-phase18.h:160
#define EXPECT_K02_INTERIOR
Definition raster-expected-phase18.h:103
#define EXPECT_K05_TOP_FAR
Definition raster-expected-phase18.h:134
#define EXPECT_K02_TOP_NEAR
Definition raster-expected-phase18.h:101
#define EXPECT_K02_TOP_FAR
Definition raster-expected-phase18.h:104
#define EXPECT_K01_VERTEX
Definition raster-expected-phase18.h:85
#define EXPECT_K03_VERTEX
Definition raster-expected-phase18.h:115
#define EXPECT_K08_VERTEX
Definition raster-expected-phase18.h:145
#define EXPECT_K08_INTERIOR
Definition raster-expected-phase18.h:148
#define EXPECT_K02_LEFT_NEAR
Definition raster-expected-phase18.h:102
#define EXPECT_K03_TOP_NEAR
Definition raster-expected-phase18.h:116
#define EXPECT_K02_VERTEX
Definition raster-expected-phase18.h:100
#define EXPECT_K08_TOP_FAR
Definition raster-expected-phase18.h:149
#define EXPECT_K01_TOP_FAR
Definition raster-expected-phase18.h:89
#define EXPECT_K16_TOP_NEAR
Definition raster-expected-phase18.h:161
#define EXPECT_K03_TOP_FAR
Definition raster-expected-phase18.h:119
#define EXPECT_K05_LEFT_NEAR
Definition raster-expected-phase18.h:132
#define EXPECT_K05_INTERIOR
Definition raster-expected-phase18.h:133
#define EXPECT_K16_TOP_FAR
Definition raster-expected-phase18.h:164
#define EXPECT_K01_INTERIOR
Definition raster-expected-phase18.h:88
#define TEX17_TY
Definition texture-fixture-phase17.h:58
#define TEX17_TPAGE
Definition texture-fixture-phase17.h:65
#define TEX17_TX
Definition texture-fixture-phase17.h:57
#define PHASE17_ASSERT_PIXEL_EQ(expected, x_, y_)
Definition texture-fixture-phase17.h:102
#define TEX17_CLUT_FIELD
Definition texture-fixture-phase17.h:66
#define TEX_MOD_NEUTRAL
Definition texture-fixtures.h:328