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texture-window.c
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1/*
2
3MIT License
4
5Copyright (c) 2026 PCSX-Redux authors
6
7Permission is hereby granted, free of charge, to any person obtaining a copy
8of this software and associated documentation files (the "Software"), to deal
9in the Software without restriction, including without limitation the rights
10to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11copies of the Software, and to permit persons to whom the Software is
12furnished to do so, subject to the following conditions:
13
14The above copyright notice and this permission notice shall be included in all
15copies or substantial portions of the Software.
16
17THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23SOFTWARE.
24
25*/
26
27// Texture window mask + offset behavior. GP0(E2) sets:
28// bits 0-4 mask_x (5-bit, in 8-texel units)
29// bits 5-9 mask_y
30// bits 10-14 offset_x
31// bits 15-19 offset_y
32//
33// Sampling formula (per psx-spx):
34// texel.u = (u AND NOT (mask.u * 8)) OR ((offset.u * 8) AND (mask.u * 8))
35// texel.v = same for v
36//
37// Mask bits set in mask.u force those high bits of u to be taken from
38// offset.u (each unit = 8 texels). Mask=0 means no windowing.
39//
40// These tests use the 4-bit CLUT fixture (16 distinct texels, u=0..15
41// per pattern row) at TEX4_TPAGE. With mask.u=0x01 (8-texel unit), bit
42// 3 of u gets forced to bit 3 of offset.u*8. So:
43// mask.u=0x01, offset.u=0x00 -> u with bit 3 cleared
44// (u=8..15 all collapse to texel u=0..7)
45// mask.u=0x01, offset.u=0x01 -> u with bit 3 set (u=0..7 collapse to 8..15)
46
48
49// Texture-window test setup: 4-bit triangle large enough to span 16
50// texel positions horizontally, with chosen E2 window state.
51static void drawTexWindowTri(uint8_t mask_x, uint8_t off_x) {
52 rasterReset();
53 rasterClearTestRegion(0, 0, 32, 16);
54 setTexpage(TEX4_TX, TEX4_TY, 0);
55 setTextureWindow(mask_x, 0, off_x, 0);
56 /* Triangle (0,0)-(16,0)-(0,8), UV (0,0)-(16,0)-(0,8). At pixel
57 (x, y), sample texel (x, y) -> window-filter -> CLUT[filtered_u]. */
58 rasterTexTri(TEX_MOD_NEUTRAL,
59 0, 0, 0, 0,
60 16, 0, 16, 0,
61 0, 8, 0, 8,
63 rasterFlushPrimitive();
64}
65
66) // CESTER_BODY
67
68// --------------------------------------------------------------------------
69// mask_x = 0, offset_x = 0: identity (no windowing)
70// --------------------------------------------------------------------------
71// Already covered by phase-4a's texture-basic.c. Skipping duplicates.
72
73// --------------------------------------------------------------------------
74// mask_x = 0x01 (= 8-texel-unit mask), offset_x = 0
75// filtered_u = u & ~0x08 = u with bit 3 cleared
76// u=0..7 -> texel 0..7
77// u=8..15 -> texel 0..7 (bit 3 cleared maps 8->0, 9->1, ..., 15->7)
78// --------------------------------------------------------------------------
79
80CESTER_TEST(texwin_mask01_off00_pixel_0_0, gpu_raster_phase4,
81 drawTexWindowTri(0x01, 0x00);
82 /* u=0, filtered=0, CLUT[0]. But CLUT[0] is texel 0 from
83 expectedClut4Color(0) = vram555(0, 31, 0). NOTE: at (0,0) this
84 reads as transparent if texel value happens to be 0x0000 (after
85 CLUT lookup). CLUT[0] = vram555(0, 31, 0) = 0x03E0 != 0x0000,
86 so the pixel SHOULD be drawn. */
87 ASSERT_PIXEL_EQ(expectedClut4Color(0), 0, 0);
88)
89
90CESTER_TEST(texwin_mask01_off00_pixel_7_0_last_unwrapped, gpu_raster_phase4,
91 drawTexWindowTri(0x01, 0x00);
92 /* u=7, filtered=7, CLUT[7]. */
93 ASSERT_PIXEL_EQ(expectedClut4Color(7), 7, 0);
94)
95
96CESTER_TEST(texwin_mask01_off00_pixel_8_0_wrapped_to_0, gpu_raster_phase4,
97 drawTexWindowTri(0x01, 0x00);
98 /* u=8, filtered=8&~8=0, CLUT[0]. So pixel 8 samples same texel as
99 pixel 0. */
100 ASSERT_PIXEL_EQ(expectedClut4Color(0), 8, 0);
101)
102
103CESTER_TEST(texwin_mask01_off00_pixel_11_0_wrapped_to_3, gpu_raster_phase4,
104 drawTexWindowTri(0x01, 0x00);
105 /* u=11=0xB, filtered=0xB&~0x8=0x3, CLUT[3]. */
106 ASSERT_PIXEL_EQ(expectedClut4Color(3), 11, 0);
107)
108
109CESTER_TEST(texwin_mask01_off00_pixel_15_0_wrapped_to_7, gpu_raster_phase4,
110 drawTexWindowTri(0x01, 0x00);
111 /* u=15=0xF, filtered=0xF&~0x8=0x7, CLUT[7]. */
112 ASSERT_PIXEL_EQ(expectedClut4Color(7), 15, 0);
113)
114
115// --------------------------------------------------------------------------
116// mask_x = 0x01, offset_x = 0x01: bit 3 forced to 1
117// filtered_u = (u & ~0x08) | (0x08) = u with bit 3 SET
118// u=0..7 -> 0x08..0x0F (texels 8..15)
119// u=8..15 -> texels 8..15
120// --------------------------------------------------------------------------
121
122CESTER_TEST(texwin_mask01_off01_pixel_0_0_forced_to_8, gpu_raster_phase4,
123 drawTexWindowTri(0x01, 0x01);
124 /* u=0, filtered=0|8=8, CLUT[8]. */
125 ASSERT_PIXEL_EQ(expectedClut4Color(8), 0, 0);
126)
127
128CESTER_TEST(texwin_mask01_off01_pixel_3_0_forced_to_b, gpu_raster_phase4,
129 drawTexWindowTri(0x01, 0x01);
130 /* u=3, filtered=3|8=0xB, CLUT[0xB]. */
131 ASSERT_PIXEL_EQ(expectedClut4Color(0x0b), 3, 0);
132)
133
134CESTER_TEST(texwin_mask01_off01_pixel_8_0_already_set, gpu_raster_phase4,
135 drawTexWindowTri(0x01, 0x01);
136 /* u=8, filtered=8 (bit 3 already set), CLUT[8]. */
137 ASSERT_PIXEL_EQ(expectedClut4Color(8), 8, 0);
138)
139
140// --------------------------------------------------------------------------
141// mask_x = 0x03 (= 24-bit mask = bits 3,4 of u): bits 3-4 forced from offset
142// With offset_x=0: filtered_u = u & ~0x18 (bits 3 and 4 cleared)
143// u=0..7 -> 0..7
144// u=8..15 -> 0..7 (bit 3 cleared)
145// (Same as mask=0x01 for u in 0..15 since bit 4 doesn't apply yet.)
146// We test u values where bit 4 would matter at higher u, but my 4-bit
147// fixture only covers u=0..15. So just one probe to characterize.
148// --------------------------------------------------------------------------
149
150CESTER_TEST(texwin_mask03_off00_pixel_13_0, gpu_raster_phase4,
151 drawTexWindowTri(0x03, 0x00);
152 /* u=13=0xD, filtered=0xD & ~0x18 = 5, CLUT[5]. */
153 ASSERT_PIXEL_EQ(expectedClut4Color(5), 13, 0);
154)
CESTER_BODY(static int s_got40;static int s_got80;static uint32_t s_cause;static uint32_t s_epc;static uint32_t s_from;static uint32_t *s_resume;static uint32_t *s_regs;static uint32_t(*s_customhandler)()=NULL;static uint32_t s_oldIMASK;static uint32_t s_oldDPCR;static uint32_t s_oldDICR;uint32_t handler(uint32_t *regs, uint32_t from) { if(from==0x40) s_got40=1;if(from==0x80) s_got80=1;uint32_t cause;uint32_t epc;s_from=from;asm("mfc0 %0, $13\nnop\nmfc0 %1, $14\nnop" :"=r"(cause), "=r"(epc));s_cause=cause;s_epc=epc;if(s_customhandler) { return s_customhandler();} else { return s_resume ?((uint32_t) s_resume) :(epc+4);} } void installExceptionHandlers(uint32_t(*handler)(uint32_t *regs, uint32_t from));void uninstallExceptionHandlers();uint32_t branchbranch1();uint32_t branchbranch2();uint32_t jumpjump1();uint32_t jumpjump2();uint32_t cpu_LWR_LWL_half(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_nodelay(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_delayed(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_load_different(uint32_t buff[], uint32_t initial);uint32_t cpu_LW_LWR(uint32_t buff[], uint32_t initial);uint32_t cpu_delayed_load(uint32_t buff[], uint32_t override);uint32_t cpu_delayed_load_cancelled(uint32_t buff[], uint32_t override);uint64_t cpu_delayed_load_load(uint32_t buff[], uint32_t override);uint32_t linkandload();uint32_t lwandlink();uint32_t nolink();static int s_interruptsWereEnabled;) CESTER_BEFORE_EACH(cpu_tests
CESTER_TEST(cpu_cop0_basic_write_bp, cpu_tests, uint32_t expectedEPC;uint32_t t;volatile uint32_t *ptr=(volatile uint32_t *) 0x58; *ptr=1;__asm__ volatile("" " lui %0, 0b1100101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0xfffffff0\n" " mtc0 %0, $9\n" :"=r"(t));cester_assert_uint_eq(1, *ptr);__asm__ volatile("la %0, 1f\n1:\nsw $0, 0x58($0)" :"=r"(expectedEPC));__asm__ volatile("mtc0 $0, $7\n");cester_assert_uint_eq(0, *ptr);cester_assert_uint_eq(1, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0x40, s_from);cester_assert_uint_eq(expectedEPC, s_epc);) CESTER_TEST(cpu_cop0_kseg_write_bp
#define ASSERT_PIXEL_EQ(expected, x_, y_)
Definition raster-helpers.h:472
#define CLUT4_FIELD
Definition texture-fixtures.h:83
#define TEX_MOD_NEUTRAL
Definition texture-fixtures.h:328
#define TEX4_TY
Definition texture-fixtures.h:56
#define TEX4_TX
Definition texture-fixtures.h:55
#define TEX4_TPAGE
Definition texture-fixtures.h:102