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dither-characterization.c
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1/*
2
3MIT License
4
5Copyright (c) 2026 PCSX-Redux authors
6
7Permission is hereby granted, free of charge, to any person obtaining a copy
8of this software and associated documentation files (the "Software"), to deal
9in the Software without restriction, including without limitation the rights
10to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11copies of the Software, and to permit persons to whom the Software is
12furnished to do so, subject to the following conditions:
13
14The above copyright notice and this permission notice shall be included in all
15copies or substantial portions of the Software.
16
17THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23SOFTWARE.
24
25*/
26
27// Dither characterization. Each draw call below produces a CONSTANT-
28// color triangle (all three vertices the same 24-bit GP0 color) under
29// gouraud + dither on. Input color is constant across every pixel,
30// so any per-pixel output difference is the dither table offset at
31// that screen-space position.
32//
33// rgb24(R8, G8, B8) builds the 24-bit GP0 command color in the
34// canonical wire layout: bits 0-7 = R, 8-15 = G, 16-23 = B.
35
36CESTER_BODY(
37
38static inline uint32_t rgb24(uint8_t r, uint8_t g, uint8_t b) {
39 return (uint32_t)r | ((uint32_t)g << 8) | ((uint32_t)b << 16);
40}
41
42// Draw a 32x32 constant-color gouraud triangle at (x0, y0).
43// All three vertices share the same 24-bit color so per-pixel input
44// is constant. Dither bit (E1[9]) is set before the draw.
45static void drawDitherConstTri(uint32_t color24, int16_t x0, int16_t y0) {
46 rasterReset();
47 rasterClearTestRegion(0, 0, 64, 64);
48 rasterSetDither(1);
49 rasterGouraudTri(color24, x0, y0,
50 color24, (int16_t)(x0 + 31), y0,
51 color24, x0, (int16_t)(y0 + 31));
52 rasterFlushPrimitive();
53 rasterSetDither(0);
54}
55
56// Standard probe origin: (0, 0) for the canonical capture series.
57// The 4x4 Bayer cell at (cx, cy) lands at probe (8 + cx, 8 + cy)
58// when the triangle is at origin and dither table is screen-space-
59// anchored to (0, 0).
60static void drawCanonicalAt(uint32_t color24) {
61 drawDitherConstTri(color24, 0, 0);
62}
63
64) // CESTER_BODY
65
66// ============================================================================
67// DT_BAYER: 4x4 Bayer capture at mid-gray (R=G=B=128). Probes all 16
68// cells of one period at (8..11, 8..11). The output at each cell is
69// the dither-altered VRAM value for input (R=128, G=128, B=128).
70// Subtracting the nominal mid-gray (vram555(16, 16, 16) = 0x4210)
71// gives the per-cell offset map at this base color.
72// ============================================================================
73
74CESTER_TEST(dt_bayer_mid_8_8, gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_8_8, 8, 8); )
75CESTER_TEST(dt_bayer_mid_9_8, gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_9_8, 9, 8); )
76CESTER_TEST(dt_bayer_mid_10_8, gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_10_8, 10, 8); )
77CESTER_TEST(dt_bayer_mid_11_8, gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_11_8, 11, 8); )
78CESTER_TEST(dt_bayer_mid_8_9, gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_8_9, 8, 9); )
79CESTER_TEST(dt_bayer_mid_9_9, gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_9_9, 9, 9); )
80CESTER_TEST(dt_bayer_mid_10_9, gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_10_9, 10, 9); )
81CESTER_TEST(dt_bayer_mid_11_9, gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_11_9, 11, 9); )
82CESTER_TEST(dt_bayer_mid_8_10, gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_8_10, 8, 10); )
83CESTER_TEST(dt_bayer_mid_9_10, gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_9_10, 9, 10); )
84CESTER_TEST(dt_bayer_mid_10_10,gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_10_10,10, 10); )
85CESTER_TEST(dt_bayer_mid_11_10,gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_11_10,11, 10); )
86CESTER_TEST(dt_bayer_mid_8_11, gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_8_11, 8, 11); )
87CESTER_TEST(dt_bayer_mid_9_11, gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_9_11, 9, 11); )
88CESTER_TEST(dt_bayer_mid_10_11,gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_10_11,10, 11); )
89CESTER_TEST(dt_bayer_mid_11_11,gpu_raster_phase11, drawCanonicalAt(rgb24(128, 128, 128)); ASSERT_PIXEL_EQ(DT_BAYER_MID_11_11,11, 11); )
90
91// ============================================================================
92// DT_BASE_R: R-only base color sweep. G=0, B=0 across all 16 cells at
93// base R = 0x40, 0x80, 0xC0. Together with DT_SAT_R series this gives
94// a 5-base sweep on the R channel: 0x04 (near-min), 0x40, 0x80, 0xC0,
95// 0xFC (near-max). If the dither table is additive across base color,
96// each cell's offset (output_R - nominal_R) should be the same across
97// bases. If it's base-dependent (multiplicative or LUT-based), the
98// per-base offsets diverge.
99// ============================================================================
100
101CESTER_TEST(dt_base_r40_8_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_8_8, 8, 8); )
102CESTER_TEST(dt_base_r40_9_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_9_8, 9, 8); )
103CESTER_TEST(dt_base_r40_10_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_10_8, 10, 8); )
104CESTER_TEST(dt_base_r40_11_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_11_8, 11, 8); )
105CESTER_TEST(dt_base_r40_8_9, gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_8_9, 8, 9); )
106CESTER_TEST(dt_base_r40_9_9, gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_9_9, 9, 9); )
107CESTER_TEST(dt_base_r40_10_9, gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_10_9, 10, 9); )
108CESTER_TEST(dt_base_r40_11_9, gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_11_9, 11, 9); )
109CESTER_TEST(dt_base_r40_8_10, gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_8_10, 8, 10); )
110CESTER_TEST(dt_base_r40_9_10, gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_9_10, 9, 10); )
111CESTER_TEST(dt_base_r40_10_10,gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_10_10,10, 10); )
112CESTER_TEST(dt_base_r40_11_10,gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_11_10,11, 10); )
113CESTER_TEST(dt_base_r40_8_11, gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_8_11, 8, 11); )
114CESTER_TEST(dt_base_r40_9_11, gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_9_11, 9, 11); )
115CESTER_TEST(dt_base_r40_10_11,gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_10_11,10, 11); )
116CESTER_TEST(dt_base_r40_11_11,gpu_raster_phase11, drawCanonicalAt(rgb24(0x40, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R40_11_11,11, 11); )
117
118CESTER_TEST(dt_base_r80_8_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_8_8, 8, 8); )
119CESTER_TEST(dt_base_r80_9_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_9_8, 9, 8); )
120CESTER_TEST(dt_base_r80_10_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_10_8, 10, 8); )
121CESTER_TEST(dt_base_r80_11_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_11_8, 11, 8); )
122CESTER_TEST(dt_base_r80_8_9, gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_8_9, 8, 9); )
123CESTER_TEST(dt_base_r80_9_9, gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_9_9, 9, 9); )
124CESTER_TEST(dt_base_r80_10_9, gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_10_9, 10, 9); )
125CESTER_TEST(dt_base_r80_11_9, gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_11_9, 11, 9); )
126CESTER_TEST(dt_base_r80_8_10, gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_8_10, 8, 10); )
127CESTER_TEST(dt_base_r80_9_10, gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_9_10, 9, 10); )
128CESTER_TEST(dt_base_r80_10_10,gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_10_10,10, 10); )
129CESTER_TEST(dt_base_r80_11_10,gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_11_10,11, 10); )
130CESTER_TEST(dt_base_r80_8_11, gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_8_11, 8, 11); )
131CESTER_TEST(dt_base_r80_9_11, gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_9_11, 9, 11); )
132CESTER_TEST(dt_base_r80_10_11,gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_10_11,10, 11); )
133CESTER_TEST(dt_base_r80_11_11,gpu_raster_phase11, drawCanonicalAt(rgb24(0x80, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_R80_11_11,11, 11); )
134
135CESTER_TEST(dt_base_rc0_8_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_8_8, 8, 8); )
136CESTER_TEST(dt_base_rc0_9_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_9_8, 9, 8); )
137CESTER_TEST(dt_base_rc0_10_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_10_8, 10, 8); )
138CESTER_TEST(dt_base_rc0_11_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_11_8, 11, 8); )
139CESTER_TEST(dt_base_rc0_8_9, gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_8_9, 8, 9); )
140CESTER_TEST(dt_base_rc0_9_9, gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_9_9, 9, 9); )
141CESTER_TEST(dt_base_rc0_10_9, gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_10_9, 10, 9); )
142CESTER_TEST(dt_base_rc0_11_9, gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_11_9, 11, 9); )
143CESTER_TEST(dt_base_rc0_8_10, gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_8_10, 8, 10); )
144CESTER_TEST(dt_base_rc0_9_10, gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_9_10, 9, 10); )
145CESTER_TEST(dt_base_rc0_10_10,gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_10_10,10, 10); )
146CESTER_TEST(dt_base_rc0_11_10,gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_11_10,11, 10); )
147CESTER_TEST(dt_base_rc0_8_11, gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_8_11, 8, 11); )
148CESTER_TEST(dt_base_rc0_9_11, gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_9_11, 9, 11); )
149CESTER_TEST(dt_base_rc0_10_11,gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_10_11,10, 11); )
150CESTER_TEST(dt_base_rc0_11_11,gpu_raster_phase11, drawCanonicalAt(rgb24(0xc0, 0, 0)); ASSERT_PIXEL_EQ(DT_BASE_RC0_11_11,11, 11); )
151
152// ============================================================================
153// DT_CHAN_G / DT_CHAN_B: 4-cell controls at G-only and B-only base 128.
154// Confirms the dither table is channel-independent - the per-cell offset
155// at (8, 8) should be the same for R-only, G-only, and B-only base 128.
156// ============================================================================
157
158CESTER_TEST(dt_chan_g80_8_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0, 0x80, 0)); ASSERT_PIXEL_EQ(DT_CHAN_G80_8_8, 8, 8); )
159CESTER_TEST(dt_chan_g80_9_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0, 0x80, 0)); ASSERT_PIXEL_EQ(DT_CHAN_G80_9_8, 9, 8); )
160CESTER_TEST(dt_chan_g80_10_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0, 0x80, 0)); ASSERT_PIXEL_EQ(DT_CHAN_G80_10_8, 10, 8); )
161CESTER_TEST(dt_chan_g80_11_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0, 0x80, 0)); ASSERT_PIXEL_EQ(DT_CHAN_G80_11_8, 11, 8); )
162
163CESTER_TEST(dt_chan_b80_8_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0, 0, 0x80)); ASSERT_PIXEL_EQ(DT_CHAN_B80_8_8, 8, 8); )
164CESTER_TEST(dt_chan_b80_9_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0, 0, 0x80)); ASSERT_PIXEL_EQ(DT_CHAN_B80_9_8, 9, 8); )
165CESTER_TEST(dt_chan_b80_10_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0, 0, 0x80)); ASSERT_PIXEL_EQ(DT_CHAN_B80_10_8, 10, 8); )
166CESTER_TEST(dt_chan_b80_11_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0, 0, 0x80)); ASSERT_PIXEL_EQ(DT_CHAN_B80_11_8, 11, 8); )
167
168// ============================================================================
169// DT_POS: position sweep. Same constant-color mid-gray triangle at
170// different (x, y) origins. Probe a fixed screen-space pixel under
171// each triangle. If dither is screen-space-anchored to (0, 0), the
172// captured value at screen-space (16, 16) should be the same
173// regardless of which triangle covers it. If it's triangle-relative,
174// the value varies with origin offset.
175//
176// Triangles at:
177// POS_00: origin (0, 0), probe (16, 16)
178// POS_04: origin (0, 4), probe (16, 16) - shifted +4Y
179// POS_40: origin (4, 0), probe (16, 16) - shifted +4X
180// POS_44: origin (4, 4), probe (16, 16) - shifted (+4, +4)
181//
182// All four are mid-gray (R=G=B=128); only the triangle origin differs.
183// If the 4-cell shift moves the captured pixel into a different Bayer
184// cell, screen-space anchoring is confirmed. If all four read the same
185// value, the dither table is anchored to the triangle's start vertex.
186// ============================================================================
187
188CESTER_TEST(dt_pos_00_at_16_16, gpu_raster_phase11,
189 drawDitherConstTri(rgb24(128, 128, 128), 0, 0);
190 ASSERT_PIXEL_EQ(DT_POS_00_AT_16_16, 16, 16);
191)
192CESTER_TEST(dt_pos_04_at_16_16, gpu_raster_phase11,
193 drawDitherConstTri(rgb24(128, 128, 128), 0, 4);
194 ASSERT_PIXEL_EQ(DT_POS_04_AT_16_16, 16, 16);
195)
196CESTER_TEST(dt_pos_40_at_16_16, gpu_raster_phase11,
197 drawDitherConstTri(rgb24(128, 128, 128), 4, 0);
198 ASSERT_PIXEL_EQ(DT_POS_40_AT_16_16, 16, 16);
199)
200CESTER_TEST(dt_pos_44_at_16_16, gpu_raster_phase11,
201 drawDitherConstTri(rgb24(128, 128, 128), 4, 4);
202 ASSERT_PIXEL_EQ(DT_POS_44_AT_16_16, 16, 16);
203)
204
205// ============================================================================
206// DT_SAT_LOW: near-min base (R=4). Dither cells that would push below
207// 0 must clamp at 0 - not wrap. Probes 4 cells.
208// ============================================================================
209
210CESTER_TEST(dt_sat_low_r04_8_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0x04, 0, 0)); ASSERT_PIXEL_EQ(DT_SAT_LOW_R04_8_8, 8, 8); )
211CESTER_TEST(dt_sat_low_r04_9_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0x04, 0, 0)); ASSERT_PIXEL_EQ(DT_SAT_LOW_R04_9_8, 9, 8); )
212CESTER_TEST(dt_sat_low_r04_10_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0x04, 0, 0)); ASSERT_PIXEL_EQ(DT_SAT_LOW_R04_10_8, 10, 8); )
213CESTER_TEST(dt_sat_low_r04_11_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0x04, 0, 0)); ASSERT_PIXEL_EQ(DT_SAT_LOW_R04_11_8, 11, 8); )
214
215// ============================================================================
216// DT_SAT_HIGH: near-max base (R=0xFC). Dither cells that would push
217// above 255 must clamp at 31 in 5-bit space.
218// ============================================================================
219
220CESTER_TEST(dt_sat_high_rfc_8_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0xfc, 0, 0)); ASSERT_PIXEL_EQ(DT_SAT_HIGH_RFC_8_8, 8, 8); )
221CESTER_TEST(dt_sat_high_rfc_9_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0xfc, 0, 0)); ASSERT_PIXEL_EQ(DT_SAT_HIGH_RFC_9_8, 9, 8); )
222CESTER_TEST(dt_sat_high_rfc_10_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0xfc, 0, 0)); ASSERT_PIXEL_EQ(DT_SAT_HIGH_RFC_10_8, 10, 8); )
223CESTER_TEST(dt_sat_high_rfc_11_8, gpu_raster_phase11, drawCanonicalAt(rgb24(0xfc, 0, 0)); ASSERT_PIXEL_EQ(DT_SAT_HIGH_RFC_11_8, 11, 8); )
224
225// ============================================================================
226// DT_SAT_CROSS: probes the cells where the Bayer offset would push
227// the dithered value across the channel boundary, distinguishing
228// clamp-vs-wrap policy.
229//
230// Cells (0, 0) and (2, 2) have offset -4 - at screen positions (8, 8)
231// and (10, 10). Cells (2, 1) and (0, 3) have offset +3 - at screen
232// (10, 9) and (8, 11).
233// ============================================================================
234
235CESTER_TEST(dt_sat_cross_under_r3_8_8, gpu_raster_phase11,
236 /* R=3 at cell offset -4 = -1 raw. Clamp: 0 -> R5=0. Wrap: 255 -> R5=31. */
237 drawCanonicalAt(rgb24(0x03, 0, 0));
238 ASSERT_PIXEL_EQ(DT_SAT_CROSS_UNDER_R3_8_8, 8, 8);
239)
240CESTER_TEST(dt_sat_cross_under_r3_10_10, gpu_raster_phase11,
241 drawCanonicalAt(rgb24(0x03, 0, 0));
242 ASSERT_PIXEL_EQ(DT_SAT_CROSS_UNDER_R3_10_10, 10, 10);
243)
244CESTER_TEST(dt_sat_cross_land_r4_8_8, gpu_raster_phase11,
245 /* R=4 at cell offset -4 = 0. Output R5=0 regardless of policy. */
246 drawCanonicalAt(rgb24(0x04, 0, 0));
247 ASSERT_PIXEL_EQ(DT_SAT_CROSS_LAND_R4_8_8, 8, 8);
248)
249CESTER_TEST(dt_sat_cross_over_r255_10_9, gpu_raster_phase11,
250 /* R=255 at cell offset +3 = 258 raw. Clamp: 255 -> R5=31. Wrap: 2 -> R5=0. */
251 drawCanonicalAt(rgb24(0xff, 0, 0));
252 ASSERT_PIXEL_EQ(DT_SAT_CROSS_OVER_R255_10_9, 10, 9);
253)
254CESTER_TEST(dt_sat_cross_over_r255_8_11, gpu_raster_phase11,
255 drawCanonicalAt(rgb24(0xff, 0, 0));
256 ASSERT_PIXEL_EQ(DT_SAT_CROSS_OVER_R255_8_11, 8, 11);
257)
258CESTER_TEST(dt_sat_cross_land_r252_10_9, gpu_raster_phase11,
259 /* R=252 at cell offset +3 = 255 exactly. Output R5=31 regardless. */
260 drawCanonicalAt(rgb24(0xfc, 0, 0));
261 ASSERT_PIXEL_EQ(DT_SAT_CROSS_LAND_R252_10_9, 10, 9);
262)
CESTER_BODY
CESTER_BODY(static int s_got40;static int s_got80;static uint32_t s_cause;static uint32_t s_epc;static uint32_t s_from;static uint32_t *s_resume;static uint32_t *s_regs;static uint32_t(*s_customhandler)()=NULL;static uint32_t s_oldIMASK;static uint32_t s_oldDPCR;static uint32_t s_oldDICR;uint32_t handler(uint32_t *regs, uint32_t from) { if(from==0x40) s_got40=1;if(from==0x80) s_got80=1;uint32_t cause;uint32_t epc;s_from=from;asm("mfc0 %0, $13\nnop\nmfc0 %1, $14\nnop" :"=r"(cause), "=r"(epc));s_cause=cause;s_epc=epc;if(s_customhandler) { return s_customhandler();} else { return s_resume ?((uint32_t) s_resume) :(epc+4);} } void installExceptionHandlers(uint32_t(*handler)(uint32_t *regs, uint32_t from));void uninstallExceptionHandlers();uint32_t branchbranch1();uint32_t branchbranch2();uint32_t jumpjump1();uint32_t jumpjump2();uint32_t cpu_LWR_LWL_half(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_nodelay(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_delayed(uint32_t buff[], uint32_t initial);uint32_t cpu_LWR_LWL_load_different(uint32_t buff[], uint32_t initial);uint32_t cpu_LW_LWR(uint32_t buff[], uint32_t initial);uint32_t cpu_delayed_load(uint32_t buff[], uint32_t override);uint32_t cpu_delayed_load_cancelled(uint32_t buff[], uint32_t override);uint64_t cpu_delayed_load_load(uint32_t buff[], uint32_t override);uint32_t linkandload();uint32_t lwandlink();uint32_t nolink();static int s_interruptsWereEnabled;) CESTER_BEFORE_EACH(cpu_tests
CESTER_TEST
CESTER_TEST(cpu_cop0_basic_write_bp, cpu_tests, uint32_t expectedEPC;uint32_t t;volatile uint32_t *ptr=(volatile uint32_t *) 0x58; *ptr=1;__asm__ volatile("" " lui %0, 0b1100101010000000\n" " mtc0 %0, $7\n" " li %0, 0x58\n" " mtc0 %0, $5\n" " li %0, 0xfffffff0\n" " mtc0 %0, $9\n" :"=r"(t));cester_assert_uint_eq(1, *ptr);__asm__ volatile("la %0, 1f\n1:\nsw $0, 0x58($0)" :"=r"(expectedEPC));__asm__ volatile("mtc0 $0, $7\n");cester_assert_uint_eq(0, *ptr);cester_assert_uint_eq(1, s_got40);cester_assert_uint_eq(0, s_got80);cester_assert_uint_eq(0x40, s_from);cester_assert_uint_eq(expectedEPC, s_epc);) CESTER_TEST(cpu_cop0_kseg_write_bp
r
uint32_t r
Definition cpu.c:222
g
uint8_t g
Definition gte-depthcue.c:38
b
uint8_t b
Definition gte-depthcue.c:39
DT_BAYER_MID_8_11
#define DT_BAYER_MID_8_11
Definition raster-expected-phase11.h:94
DT_BASE_RC0_11_11
#define DT_BASE_RC0_11_11
Definition raster-expected-phase11.h:155
DT_BAYER_MID_10_8
#define DT_BAYER_MID_10_8
Definition raster-expected-phase11.h:84
DT_SAT_HIGH_RFC_8_8
#define DT_SAT_HIGH_RFC_8_8
Definition raster-expected-phase11.h:213
DT_BAYER_MID_11_11
#define DT_BAYER_MID_11_11
Definition raster-expected-phase11.h:97
DT_POS_04_AT_16_16
#define DT_POS_04_AT_16_16
Definition raster-expected-phase11.h:191
DT_SAT_CROSS_LAND_R252_10_9
#define DT_SAT_CROSS_LAND_R252_10_9
Definition raster-expected-phase11.h:240
DT_BAYER_MID_10_11
#define DT_BAYER_MID_10_11
Definition raster-expected-phase11.h:96
DT_CHAN_B80_11_8
#define DT_CHAN_B80_11_8
Definition raster-expected-phase11.h:171
DT_BASE_R80_11_11
#define DT_BASE_R80_11_11
Definition raster-expected-phase11.h:138
DT_BASE_R40_8_11
#define DT_BASE_R40_8_11
Definition raster-expected-phase11.h:118
DT_BASE_R40_9_10
#define DT_BASE_R40_9_10
Definition raster-expected-phase11.h:115
DT_BAYER_MID_10_9
#define DT_BAYER_MID_10_9
Definition raster-expected-phase11.h:88
DT_BASE_R40_9_9
#define DT_BASE_R40_9_9
Definition raster-expected-phase11.h:111
DT_BAYER_MID_10_10
#define DT_BAYER_MID_10_10
Definition raster-expected-phase11.h:92
DT_BASE_R80_8_9
#define DT_BASE_R80_8_9
Definition raster-expected-phase11.h:127
DT_SAT_CROSS_UNDER_R3_8_8
#define DT_SAT_CROSS_UNDER_R3_8_8
Definition raster-expected-phase11.h:235
DT_BASE_R80_10_9
#define DT_BASE_R80_10_9
Definition raster-expected-phase11.h:129
DT_BASE_R40_10_9
#define DT_BASE_R40_10_9
Definition raster-expected-phase11.h:112
DT_BASE_R80_10_11
#define DT_BASE_R80_10_11
Definition raster-expected-phase11.h:137
DT_BASE_R40_9_11
#define DT_BASE_R40_9_11
Definition raster-expected-phase11.h:119
DT_BAYER_MID_9_8
#define DT_BAYER_MID_9_8
Definition raster-expected-phase11.h:83
DT_BASE_R80_11_8
#define DT_BASE_R80_11_8
Definition raster-expected-phase11.h:126
DT_BASE_R40_11_11
#define DT_BASE_R40_11_11
Definition raster-expected-phase11.h:121
DT_BAYER_MID_11_8
#define DT_BAYER_MID_11_8
Definition raster-expected-phase11.h:85
DT_BASE_R80_10_10
#define DT_BASE_R80_10_10
Definition raster-expected-phase11.h:133
DT_SAT_CROSS_UNDER_R3_10_10
#define DT_SAT_CROSS_UNDER_R3_10_10
Definition raster-expected-phase11.h:236
DT_SAT_HIGH_RFC_9_8
#define DT_SAT_HIGH_RFC_9_8
Definition raster-expected-phase11.h:214
DT_CHAN_G80_11_8
#define DT_CHAN_G80_11_8
Definition raster-expected-phase11.h:166
DT_BASE_RC0_8_11
#define DT_BASE_RC0_8_11
Definition raster-expected-phase11.h:152
DT_BASE_R40_11_10
#define DT_BASE_R40_11_10
Definition raster-expected-phase11.h:117
DT_BAYER_MID_8_9
#define DT_BAYER_MID_8_9
Definition raster-expected-phase11.h:86
DT_BASE_R80_10_8
#define DT_BASE_R80_10_8
Definition raster-expected-phase11.h:125
DT_BASE_R40_10_11
#define DT_BASE_R40_10_11
Definition raster-expected-phase11.h:120
DT_BASE_R80_8_11
#define DT_BASE_R80_8_11
Definition raster-expected-phase11.h:135
DT_SAT_LOW_R04_8_8
#define DT_SAT_LOW_R04_8_8
Definition raster-expected-phase11.h:205
DT_BASE_RC0_9_8
#define DT_BASE_RC0_9_8
Definition raster-expected-phase11.h:141
DT_BASE_R80_9_9
#define DT_BASE_R80_9_9
Definition raster-expected-phase11.h:128
DT_SAT_CROSS_OVER_R255_8_11
#define DT_SAT_CROSS_OVER_R255_8_11
Definition raster-expected-phase11.h:239
DT_POS_40_AT_16_16
#define DT_POS_40_AT_16_16
Definition raster-expected-phase11.h:192
DT_BASE_R40_11_9
#define DT_BASE_R40_11_9
Definition raster-expected-phase11.h:113
DT_CHAN_G80_8_8
#define DT_CHAN_G80_8_8
Definition raster-expected-phase11.h:163
DT_BASE_R40_8_8
#define DT_BASE_R40_8_8
Definition raster-expected-phase11.h:106
DT_CHAN_G80_10_8
#define DT_CHAN_G80_10_8
Definition raster-expected-phase11.h:165
DT_BAYER_MID_8_10
#define DT_BAYER_MID_8_10
Definition raster-expected-phase11.h:90
DT_BASE_RC0_11_8
#define DT_BASE_RC0_11_8
Definition raster-expected-phase11.h:143
DT_SAT_CROSS_OVER_R255_10_9
#define DT_SAT_CROSS_OVER_R255_10_9
Definition raster-expected-phase11.h:238
DT_BASE_RC0_9_10
#define DT_BASE_RC0_9_10
Definition raster-expected-phase11.h:149
DT_BASE_R40_11_8
#define DT_BASE_R40_11_8
Definition raster-expected-phase11.h:109
DT_BAYER_MID_9_9
#define DT_BAYER_MID_9_9
Definition raster-expected-phase11.h:87
DT_BASE_RC0_10_9
#define DT_BASE_RC0_10_9
Definition raster-expected-phase11.h:146
DT_CHAN_B80_10_8
#define DT_CHAN_B80_10_8
Definition raster-expected-phase11.h:170
DT_SAT_HIGH_RFC_10_8
#define DT_SAT_HIGH_RFC_10_8
Definition raster-expected-phase11.h:215
DT_BASE_R40_8_10
#define DT_BASE_R40_8_10
Definition raster-expected-phase11.h:114
DT_BASE_RC0_8_9
#define DT_BASE_RC0_8_9
Definition raster-expected-phase11.h:144
DT_BASE_R80_11_10
#define DT_BASE_R80_11_10
Definition raster-expected-phase11.h:134
DT_BASE_R40_10_8
#define DT_BASE_R40_10_8
Definition raster-expected-phase11.h:108
DT_BASE_R40_10_10
#define DT_BASE_R40_10_10
Definition raster-expected-phase11.h:116
DT_BAYER_MID_11_9
#define DT_BAYER_MID_11_9
Definition raster-expected-phase11.h:89
DT_BASE_RC0_9_11
#define DT_BASE_RC0_9_11
Definition raster-expected-phase11.h:153
DT_BASE_RC0_11_9
#define DT_BASE_RC0_11_9
Definition raster-expected-phase11.h:147
DT_BASE_RC0_10_11
#define DT_BASE_RC0_10_11
Definition raster-expected-phase11.h:154
DT_CHAN_B80_9_8
#define DT_CHAN_B80_9_8
Definition raster-expected-phase11.h:169
DT_BASE_R80_9_11
#define DT_BASE_R80_9_11
Definition raster-expected-phase11.h:136
DT_SAT_LOW_R04_11_8
#define DT_SAT_LOW_R04_11_8
Definition raster-expected-phase11.h:208
DT_SAT_HIGH_RFC_11_8
#define DT_SAT_HIGH_RFC_11_8
Definition raster-expected-phase11.h:216
DT_CHAN_G80_9_8
#define DT_CHAN_G80_9_8
Definition raster-expected-phase11.h:164
DT_BASE_RC0_10_8
#define DT_BASE_RC0_10_8
Definition raster-expected-phase11.h:142
DT_CHAN_B80_8_8
#define DT_CHAN_B80_8_8
Definition raster-expected-phase11.h:168
DT_BASE_R80_11_9
#define DT_BASE_R80_11_9
Definition raster-expected-phase11.h:130
DT_BASE_R40_9_8
#define DT_BASE_R40_9_8
Definition raster-expected-phase11.h:107
DT_POS_44_AT_16_16
#define DT_POS_44_AT_16_16
Definition raster-expected-phase11.h:193
DT_BASE_RC0_11_10
#define DT_BASE_RC0_11_10
Definition raster-expected-phase11.h:151
DT_SAT_CROSS_LAND_R4_8_8
#define DT_SAT_CROSS_LAND_R4_8_8
Definition raster-expected-phase11.h:237
DT_BASE_R80_8_8
#define DT_BASE_R80_8_8
Definition raster-expected-phase11.h:123
DT_BASE_R80_8_10
#define DT_BASE_R80_8_10
Definition raster-expected-phase11.h:131
DT_BASE_RC0_9_9
#define DT_BASE_RC0_9_9
Definition raster-expected-phase11.h:145
DT_BAYER_MID_9_10
#define DT_BAYER_MID_9_10
Definition raster-expected-phase11.h:91
DT_BASE_R80_9_10
#define DT_BASE_R80_9_10
Definition raster-expected-phase11.h:132
DT_BAYER_MID_8_8
#define DT_BAYER_MID_8_8
Definition raster-expected-phase11.h:82
DT_BASE_RC0_8_8
#define DT_BASE_RC0_8_8
Definition raster-expected-phase11.h:140
DT_BASE_R40_8_9
#define DT_BASE_R40_8_9
Definition raster-expected-phase11.h:110
DT_BASE_RC0_8_10
#define DT_BASE_RC0_8_10
Definition raster-expected-phase11.h:148
DT_SAT_LOW_R04_10_8
#define DT_SAT_LOW_R04_10_8
Definition raster-expected-phase11.h:207
DT_BAYER_MID_11_10
#define DT_BAYER_MID_11_10
Definition raster-expected-phase11.h:93
DT_BAYER_MID_9_11
#define DT_BAYER_MID_9_11
Definition raster-expected-phase11.h:95
DT_BASE_RC0_10_10
#define DT_BASE_RC0_10_10
Definition raster-expected-phase11.h:150
DT_POS_00_AT_16_16
#define DT_POS_00_AT_16_16
Definition raster-expected-phase11.h:190
DT_BASE_R80_9_8
#define DT_BASE_R80_9_8
Definition raster-expected-phase11.h:124
DT_SAT_LOW_R04_9_8
#define DT_SAT_LOW_R04_9_8
Definition raster-expected-phase11.h:206
ASSERT_PIXEL_EQ
#define ASSERT_PIXEL_EQ(expected, x_, y_)
Definition raster-helpers.h:472
uint32_t
void uint32_t(classId, spec)
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