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gte-edgecase.c
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1// Edge cases and degenerate inputs: division, overflow boundaries,
2// zero matrices, negative Z, FLAG verification per instruction.
3
4// ==========================================================================
5// Division edge cases (tested via RTPS)
6// ==========================================================================
7
8// Division by zero: SZ3=0
9CESTER_TEST(edge_div_by_zero, gte_tests,
10 gte_set_identity_rotation();
11 gte_set_translation(0, 0, 0);
12 gte_set_screen(0, 0, 200);
13 cop2_put(0, (0 << 16) | 100);
14 cop2_put(1, 0); // VZ0=0 -> SZ3=0
15 gte_clear_flag();
16 cop2_cmd(COP2_RTPS(1, 0));
17 uint32_t sz3, sxy2, flag;
18 cop2_get(19, sz3);
19 cop2_get(14, sxy2);
20 flag = gte_read_flag();
21 ramsyscall_printf("div/0: SZ3=%u SXY2=0x%08x FLAG=0x%08x\n", sz3, sxy2, flag);
22 // SZ3=0, H=200 -> H >= SZ3*2 -> division overflow (FLAG.17)
23 uint32_t f17 = (flag >> 17) & 1;
24 cester_assert_uint_eq(1, f17);
25)
26
27// H=0: zero numerator
28CESTER_TEST(edge_div_h_zero, gte_tests,
29 gte_set_identity_rotation();
30 gte_set_translation(0, 0, 0);
31 gte_set_screen(0, 0, 0); // H=0
32 cop2_put(0, (0 << 16) | 100);
33 cop2_put(1, 1000);
34 gte_clear_flag();
35 cop2_cmd(COP2_RTPS(1, 0));
36 uint32_t sxy2, flag;
37 cop2_get(14, sxy2);
38 flag = gte_read_flag();
39 int16_t sx = (int16_t)(sxy2 & 0xffff);
40 ramsyscall_printf("H=0: SX=%d FLAG=0x%08x\n", sx, flag);
41 // H=0, SZ3=1000 -> H < SZ3*2 -> no overflow, quotient = 0
42 // SX = OFX/65536 + IR1 * 0 = 0
43 cester_assert_int_eq(0, sx);
44 uint32_t f17 = (flag >> 17) & 1;
45 cester_assert_uint_eq(0, f17);
46)
47
48// Division overflow boundary: H=SZ3*2-1 (just under, no overflow)
49CESTER_TEST(edge_div_boundary_under, gte_tests,
50 gte_set_identity_rotation();
51 gte_set_translation(0, 0, 0);
52 gte_set_screen(0, 0, 199); // H=199
53 cop2_put(0, (0 << 16) | 100);
54 cop2_put(1, 100); // SZ3=100 -> H < 200 -> no overflow
55 gte_clear_flag();
56 cop2_cmd(COP2_RTPS(1, 0));
57 uint32_t flag;
58 flag = gte_read_flag();
59 uint32_t f17 = (flag >> 17) & 1;
60 ramsyscall_printf("div boundary under: H=199 SZ3=100 FLAG.17=%u\n", f17);
61 cester_assert_uint_eq(0, f17);
62)
63
64// Division overflow boundary: H=SZ3*2 (exactly at overflow)
65CESTER_TEST(edge_div_boundary_at, gte_tests,
66 gte_set_identity_rotation();
67 gte_set_translation(0, 0, 0);
68 gte_set_screen(0, 0, 200); // H=200
69 cop2_put(0, (0 << 16) | 100);
70 cop2_put(1, 100); // SZ3=100 -> H >= 200 -> overflow
71 gte_clear_flag();
72 cop2_cmd(COP2_RTPS(1, 0));
73 uint32_t flag;
74 flag = gte_read_flag();
75 uint32_t f17 = (flag >> 17) & 1;
76 ramsyscall_printf("div boundary at: H=200 SZ3=100 FLAG.17=%u\n", f17);
77 cester_assert_uint_eq(1, f17);
78)
79
80// Division overflow boundary: H=SZ3*2+1 (just over, definitely overflow)
81CESTER_TEST(edge_div_boundary_over, gte_tests,
82 gte_set_identity_rotation();
83 gte_set_translation(0, 0, 0);
84 gte_set_screen(0, 0, 201); // H=201
85 cop2_put(0, (0 << 16) | 100);
86 cop2_put(1, 100);
87 gte_clear_flag();
88 cop2_cmd(COP2_RTPS(1, 0));
89 uint32_t flag;
90 flag = gte_read_flag();
91 uint32_t f17 = (flag >> 17) & 1;
92 cester_assert_uint_eq(1, f17);
93)
94
95// ==========================================================================
96// IR saturation boundaries
97// ==========================================================================
98
99// IR at exactly 0x7FFF (max positive, no saturation)
100CESTER_TEST(edge_ir_max_no_sat, gte_tests,
101 cop2_put(8, 0x1000);
102 cop2_put(9, 0x7fff);
103 cop2_put(10, 0x7fff);
104 cop2_put(11, 0x7fff);
105 cop2_put(6, 0x00808080);
106 gte_clear_flag();
107 cop2_cmd(COP2_GPF(1, 0));
108 uint32_t ir1;
109 cop2_get(9, ir1);
110 uint32_t flag = gte_read_flag();
111 // 0x1000 * 0x7FFF >> 12 = 0x7FFF -> no saturation
112 cester_assert_uint_eq(0x7fff, ir1);
113 // FLAG.24 (IR1 sat) should NOT be set
114 uint32_t f24 = (flag >> 24) & 1;
115 cester_assert_uint_eq(0, f24);
116)
117
118// IR just over 0x7FFF (triggers saturation)
119CESTER_TEST(edge_ir_over_max, gte_tests,
120 cop2_put(8, 0x1001); // IR0 = 0x1001 (slightly > 1.0)
121 cop2_put(9, 0x7fff);
122 cop2_put(10, 0x100);
123 cop2_put(11, 0x100);
124 cop2_put(6, 0x00808080);
125 gte_clear_flag();
126 cop2_cmd(COP2_GPF(1, 0));
127 uint32_t ir1;
128 cop2_get(9, ir1);
129 uint32_t flag = gte_read_flag();
130 ramsyscall_printf("IR over max: IR1=0x%04x FLAG=0x%08x\n", ir1 & 0xffff, flag);
131 // 0x1001 * 0x7FFF >> 12 = 0x8000 -> saturates to 0x7FFF
132 cester_assert_uint_eq(0x7fff, ir1);
133 uint32_t f24 = (flag >> 24) & 1;
134 cester_assert_uint_eq(1, f24);
135)
136
137// ==========================================================================
138// MAC0 overflow boundaries
139// ==========================================================================
140
141// NCLIP with values designed to overflow MAC0
142CESTER_TEST(edge_mac0_positive_overflow, gte_tests,
143 // Maximize cross product: opposing corners of 16-bit range
144 cop2_put(12, (0x7fff << 16) | 0x7fff); // (32767, 32767)
145 cop2_put(13, (0x8000 << 16) | 0x8000); // (-32768, -32768)
146 cop2_put(14, 0x00000000); // (0, 0)
147 gte_clear_flag();
148 cop2_cmd(COP2_NCLIP);
149 int32_t mac0;
150 uint32_t flag;
151 cop2_get(24, mac0);
152 flag = gte_read_flag();
153 // SX0*(SY1-SY2) + SX1*(SY2-SY0) + SX2*(SY0-SY1)
154 // = 32767*(-32768) + (-32768)*(0-32767) + 0
155 // = -1073709056 + (-32768)*(-32767)
156 // = -1073709056 + 1073709056 = 0... hmm, that's zero
157 // Actually: 32767*(-32768-0) + (-32768)*(0-32767) + 0*(32767-(-32768))
158 // = 32767*(-32768) + (-32768)*(-32767)
159 // = -1073709056 + 1073709056 = 0
160 // Need asymmetric triangle for overflow
161 ramsyscall_printf("MAC0 overflow test: MAC0=%d FLAG=0x%08x (F16=%u F15=%u)\n",
162 mac0, flag, (flag >> 16) & 1, (flag >> 15) & 1);
163 // Cancels to zero - no actual overflow despite the test name
164 cester_assert_int_eq(0, mac0);
165 cester_assert_uint_eq(0x00000000, flag);
166)
167
168// NCLIP that actually overflows MAC0 negatively
169CESTER_TEST(edge_mac0_negative_overflow, gte_tests,
170 // (32767, 32767), (-32768, 32767), (32767, -32768)
171 cop2_put(12, (0x7fff << 16) | 0x7fff);
172 cop2_put(13, (0x7fff << 16) | 0x8000);
173 cop2_put(14, (0x8000 << 16) | 0x7fff);
174 gte_clear_flag();
175 cop2_cmd(COP2_NCLIP);
176 int32_t mac0;
177 uint32_t flag;
178 cop2_get(24, mac0);
179 flag = gte_read_flag();
180 ramsyscall_printf("MAC0 neg overflow: MAC0=%d FLAG=0x%08x\n", mac0, flag);
181 // The cross product should be large negative
182 // FLAG.15 (MAC0 negative overflow) should be set
183 cester_assert_int_eq(-131071, mac0);
184 // FLAG.16 set from intermediate positive overflow in NCLIP's chained additions
185 uint32_t f16 = (flag >> 16) & 1;
186 cester_assert_uint_eq(1, f16);
187)
188
189// ==========================================================================
190// Color saturation boundaries
191// ==========================================================================
192
193// Color output at exactly 255 (no saturation)
194CESTER_TEST(edge_color_at_255, gte_tests,
195 cop2_put(8, 0x1000);
196 cop2_put(9, 0x0ff0); // MAC1 = 0x0ff0, /16 = 255
197 cop2_put(10, 0x0ff0);
198 cop2_put(11, 0x0ff0);
199 cop2_put(6, 0x00808080);
200 gte_clear_flag();
201 cop2_cmd(COP2_GPF(1, 0));
202 uint32_t rgb2, flag;
203 cop2_get(22, rgb2);
204 flag = gte_read_flag();
205 uint32_t r_255 = rgb2 & 0xff;
206 cester_assert_uint_eq(255, r_255);
207 uint32_t f21_255 = (flag >> 21) & 1;
208 cester_assert_uint_eq(0, f21_255); // No color saturation flag
209)
210
211// Color output at 256 (saturates to 255, FLAG set)
212CESTER_TEST(edge_color_at_256, gte_tests,
213 cop2_put(8, 0x1000);
214 cop2_put(9, 0x1000); // MAC1 = 0x1000, /16 = 256 -> saturates
215 cop2_put(10, 0x100);
216 cop2_put(11, 0x100);
217 cop2_put(6, 0x00808080);
218 gte_clear_flag();
219 cop2_cmd(COP2_GPF(1, 0));
220 uint32_t rgb2, flag;
221 cop2_get(22, rgb2);
222 flag = gte_read_flag();
223 uint32_t r_256 = rgb2 & 0xff;
224 cester_assert_uint_eq(255, r_256); // saturated to 255
225 uint32_t f21_256 = (flag >> 21) & 1;
226 cester_assert_uint_eq(1, f21_256); // R saturation flag set
227)
228
229// Negative color (saturates to 0, FLAG set)
230CESTER_TEST(edge_color_negative, gte_tests,
231 cop2_put(8, 0x1000);
232 cop2_put(9, 0xffff8000); // IR1 = -32768 -> negative MAC1 -> color=0
233 cop2_put(10, 0x100);
234 cop2_put(11, 0x100);
235 cop2_put(6, 0x00808080);
236 gte_clear_flag();
237 cop2_cmd(COP2_GPF(1, 0));
238 uint32_t rgb2, flag;
239 cop2_get(22, rgb2);
240 flag = gte_read_flag();
241 uint32_t r_neg = rgb2 & 0xff;
242 cester_assert_uint_eq(0, r_neg); // clamped to 0
243 uint32_t f21_neg = (flag >> 21) & 1;
244 cester_assert_uint_eq(1, f21_neg); // Color R saturation flag
245)
246
247// ==========================================================================
248// Screen coordinate saturation
249// ==========================================================================
250
251// SX at exactly 0x3FF (max, no saturation)
252CESTER_TEST(edge_sx_at_max, gte_tests,
253 gte_set_identity_rotation();
254 gte_set_translation(0, 0, 0);
255 cop2_putc(24, 0x3ff << 16); // OFX = 0x3FF in 16.16
256 cop2_putc(25, 0);
257 cop2_putc(26, 0); // H=0 -> quotient=0 -> SX = OFX only
258 cop2_putc(27, 0);
259 cop2_putc(28, 0);
260 cop2_put(0, 0);
261 cop2_put(1, 1000);
262 gte_clear_flag();
263 cop2_cmd(COP2_RTPS(1, 0));
264 uint32_t sxy2, flag;
265 cop2_get(14, sxy2);
266 flag = gte_read_flag();
267 int16_t sx = (int16_t)(sxy2 & 0xffff);
268 cester_assert_int_eq(0x3ff, sx);
269 uint32_t f14 = (flag >> 14) & 1;
270 cester_assert_uint_eq(0, f14); // no saturation
271)
272
273// SX at 0x400 (saturates to 0x3FF)
274CESTER_TEST(edge_sx_over_max, gte_tests,
275 gte_set_identity_rotation();
276 gte_set_translation(0, 0, 0);
277 cop2_putc(24, 0x400 << 16); // OFX = 0x400
278 cop2_putc(25, 0);
279 cop2_putc(26, 0);
280 cop2_putc(27, 0);
281 cop2_putc(28, 0);
282 cop2_put(0, 0);
283 cop2_put(1, 1000);
284 gte_clear_flag();
285 cop2_cmd(COP2_RTPS(1, 0));
286 uint32_t sxy2, flag;
287 cop2_get(14, sxy2);
288 flag = gte_read_flag();
289 int16_t sx = (int16_t)(sxy2 & 0xffff);
290 cester_assert_int_eq(0x3ff, sx); // saturated
291 uint32_t f14 = (flag >> 14) & 1;
292 cester_assert_uint_eq(1, f14);
293)
294
295// SY at -0x400 (min, no saturation)
296CESTER_TEST(edge_sy_at_min, gte_tests,
297 gte_set_identity_rotation();
298 gte_set_translation(0, 0, 0);
299 cop2_putc(24, 0);
300 cop2_putc(25, (uint32_t)(-0x400) << 16); // OFY = -0x400
301 cop2_putc(26, 0);
302 cop2_putc(27, 0);
303 cop2_putc(28, 0);
304 cop2_put(0, 0);
305 cop2_put(1, 1000);
306 gte_clear_flag();
307 cop2_cmd(COP2_RTPS(1, 0));
308 uint32_t sxy2, flag;
309 cop2_get(14, sxy2);
310 flag = gte_read_flag();
311 int16_t sy = (int16_t)(sxy2 >> 16);
312 cester_assert_int_eq(-0x400, sy);
313 uint32_t f13 = (flag >> 13) & 1;
314 cester_assert_uint_eq(0, f13);
315)
316
317// ==========================================================================
318// Degenerate matrix states
319// ==========================================================================
320
321// Zero rotation matrix: everything should become translation only
322CESTER_TEST(edge_zero_matrix, gte_tests,
323 cop2_putc(0, 0);
324 cop2_putc(1, 0);
325 cop2_putc(2, 0);
326 cop2_putc(3, 0);
327 cop2_putc(4, 0);
328 gte_set_translation(100, 200, 300);
329 cop2_put(0, (0x7fff << 16) | 0x7fff); // large vertex
330 cop2_put(1, 0x7fff);
331 gte_clear_flag();
332 cop2_cmd(COP2_MVMVA(1, COP2_MX_RT, COP2_V_V0, COP2_CV_TR, 0));
333 int32_t mac1, mac2, mac3;
334 cop2_get(25, mac1);
335 cop2_get(26, mac2);
336 cop2_get(27, mac3);
337 // Zero matrix * anything = 0, plus translation
338 cester_assert_int_eq(100, mac1);
339 cester_assert_int_eq(200, mac2);
340 cester_assert_int_eq(300, mac3);
341)
342
343// Max magnitude matrix elements
344CESTER_TEST(edge_max_matrix, gte_tests,
345 cop2_putc(0, 0x7fff7fff); // R11=R12=0x7FFF
346 cop2_putc(1, 0x7fff7fff);
347 cop2_putc(2, 0x7fff7fff);
348 cop2_putc(3, 0x7fff7fff);
349 cop2_putc(4, 0x7fff);
350 gte_set_translation(0, 0, 0);
351 cop2_put(0, (0x7fff << 16) | 0x7fff);
352 cop2_put(1, 0x7fff);
353 gte_clear_flag();
354 cop2_cmd(COP2_MVMVA(1, COP2_MX_RT, COP2_V_V0, COP2_CV_NONE, 0));
355 int32_t mac1;
356 uint32_t flag;
357 cop2_get(25, mac1);
358 flag = gte_read_flag();
359 ramsyscall_printf("max matrix: MAC1=%d FLAG=0x%08x\n", mac1, flag);
360 // 3 * 0x7FFF * 0x7FFF = 3 * 1073676289 = 3221028867
361 // >> 12 = 786380, fits in 32-bit MAC. But 44-bit accumulator overflow?
362 cester_assert_int_eq(786384, mac1);
363 cester_assert_uint_eq(0x81c00000, flag);
364)
365
366// Negative Z in RTPS (behind camera)
367CESTER_TEST(edge_negative_z, gte_tests,
368 gte_set_identity_rotation();
369 gte_set_translation(0, 0, -1000); // TRZ = -1000
370 gte_set_screen(160 << 16, 120 << 16, 200);
371 cop2_put(0, (0 << 16) | 100);
372 cop2_put(1, 0); // VZ=0, MAC3 = TRZ = -1000
373 gte_clear_flag();
374 cop2_cmd(COP2_RTPS(1, 0));
375 uint32_t sz3, flag;
376 int32_t mac3;
377 cop2_get(19, sz3);
378 cop2_get(27, mac3);
379 flag = gte_read_flag();
380 ramsyscall_printf("neg Z: MAC3=%d SZ3=%u FLAG=0x%08x\n", mac3, sz3, flag);
381 // MAC3 = -1000, SZ3 should saturate to 0 (Lm_D clamps to [0, 0xFFFF])
382 cester_assert_int_eq(-1000, mac3);
383 cester_assert_uint_eq(0, sz3); // saturated
384 uint32_t f18 = (flag >> 18) & 1;
385 cester_assert_uint_eq(1, f18); // OTZ/SZ3 saturation
386)
387
388// SQR of -0x8000 (minimum 16-bit signed)
389CESTER_TEST(edge_sqr_min_negative, gte_tests,
390 cop2_put(9, 0xffff8000); // IR1 = -32768
391 cop2_put(10, 0);
392 cop2_put(11, 0);
393 gte_clear_flag();
394 cop2_cmd(COP2_SQR(0, 0));
395 int32_t mac1;
396 uint32_t flag;
397 cop2_get(25, mac1);
398 flag = gte_read_flag();
399 // (-32768)^2 = 1073741824 = 0x40000000 (fits in 32-bit signed)
400 ramsyscall_printf("SQR(-32768): MAC1=%d FLAG=0x%08x\n", mac1, flag);
401 cester_assert_int_eq(1073741824, mac1);
402)
403
404// GPL with negative MAC base
405CESTER_TEST(edge_gpl_negative_base, gte_tests,
406 cop2_put(25, -10000); // MAC1 = -10000
407 cop2_put(26, -20000);
408 cop2_put(27, -30000);
409 cop2_put(8, 0x1000); // IR0 = 1.0
410 cop2_put(9, 100);
411 cop2_put(10, 200);
412 cop2_put(11, 300);
413 cop2_put(6, 0x00808080);
414 gte_clear_flag();
415 cop2_cmd(COP2_GPL(1, 0));
416 int32_t mac1, mac2, mac3;
417 cop2_get(25, mac1);
418 cop2_get(26, mac2);
419 cop2_get(27, mac3);
420 // GPL sf=1: MAC = (old_MAC << 12 + IR0*IR) >> 12
421 // = ((-10000 << 12) + 4096*100) >> 12
422 // = (-40960000 + 409600) >> 12
423 // = -40550400 >> 12 = -9900
424 cester_assert_int_eq(-9900, mac1);
425 cester_assert_int_eq(-19800, mac2);
426 cester_assert_int_eq(-29700, mac3);
427)
428
429// ==========================================================================
430// FLAG cleared at instruction start
431// ==========================================================================
432
433// Verify FLAG is reset to 0 at the start of each GTE instruction,
434// not accumulating from previous instructions
435CESTER_TEST(edge_flag_cleared_each_instruction, gte_tests,
436 // First: trigger IR1 saturation via GPF
437 cop2_put(8, 0x1001);
438 cop2_put(9, 0x7fff);
439 cop2_put(10, 0x100);
440 cop2_put(11, 0x100);
441 cop2_put(6, 0x00808080);
442 gte_clear_flag();
443 cop2_cmd(COP2_GPF(1, 0));
444 uint32_t flag1 = gte_read_flag();
445 uint32_t f24_1 = (flag1 >> 24) & 1;
446 cester_assert_uint_eq(1, f24_1); // IR1 saturated
447
448 // Now: run a clean GPF that should NOT trigger any flags
449 cop2_put(8, 0x1000);
450 cop2_put(9, 0x100);
451 cop2_put(10, 0x100);
452 cop2_put(11, 0x100);
453 cop2_put(6, 0x00808080);
454 // Do NOT call gte_clear_flag() - the instruction should clear it itself
455 cop2_cmd(COP2_GPF(1, 0));
456 uint32_t flag2 = gte_read_flag();
457 // FLAG should be 0 - the instruction clears it at start
458 cester_assert_uint_eq(0, flag2);
459)
460
461// ==========================================================================
462// IR0 saturation boundary
463// ==========================================================================
464
465// IR0 at exactly 0x1000 (max, no saturation)
466CESTER_TEST(edge_ir0_at_max, gte_tests,
467 gte_set_identity_rotation();
468 gte_set_translation(0, 0, 0);
469 cop2_putc(24, 0);
470 cop2_putc(25, 0);
471 cop2_putc(26, 200);
472 cop2_putc(27, 0); // DQA = 0
473 cop2_putc(28, 0x1000000); // DQB = 0x1000000 -> MAC0=DQB, IR0=DQB>>12=0x1000
474 cop2_put(0, 0);
475 cop2_put(1, 1000);
476 gte_clear_flag();
477 cop2_cmd(COP2_RTPS(1, 0));
478 uint32_t ir0, flag;
479 cop2_get(8, ir0);
480 flag = gte_read_flag();
481 ramsyscall_printf("IR0 max: IR0=0x%04x FLAG=0x%08x\n", ir0 & 0xffff, flag);
482 // IR0 should be exactly 0x1000
483 uint32_t f12 = (flag >> 12) & 1;
484 cester_assert_uint_eq(0, f12); // no saturation
485)
486
487// ==========================================================================
488// OTZ saturation boundary
489// ==========================================================================
490
491// OTZ at exactly 0xFFFF (max, triggers saturation)
492CESTER_TEST(edge_otz_at_max, gte_tests,
493 // Need MAC0 >> 12 = 0xFFFF -> MAC0 = 0xFFFF << 12 = 0xFFFF000
494 // ZSF3 * (SZ1+SZ2+SZ3) = 0xFFFF000
495 // Use ZSF3 = 0x1000, SZ_sum = 0xFFFF -> each SZ = 0x5555
496 cop2_put(17, 0x5555);
497 cop2_put(18, 0x5555);
498 cop2_put(19, 0x5555);
499 cop2_putc(29, 0x1000);
500 gte_clear_flag();
501 cop2_cmd(COP2_AVSZ3);
502 uint32_t otz, flag;
503 cop2_get(7, otz);
504 flag = gte_read_flag();
505 ramsyscall_printf("OTZ max: OTZ=%u FLAG=0x%08x\n", otz, flag);
506 // 0x5555*3 = 0xFFFF, * 0x1000 = 0xFFFF000, >> 12 = 0xFFFF
507 cester_assert_uint_eq(0xffff, otz);
508)
509
510// ==========================================================================
511// Depth cue inner clamp (FC - input can go negative)
512// ==========================================================================
513
514// DPCS where FC << input color (FC-input negative, inner lm=0 clamp)
515CESTER_TEST(edge_depthcue_fc_less_than_input, gte_tests,
516 gte_set_far_color(0, 0, 0); // FC = 0 (dark fog)
517 cop2_put(6, 0x00ffffff); // RGBC: R=G=B=0xFF (bright)
518 cop2_put(8, 0x0800); // IR0 = 0.5
519 gte_clear_flag();
520 cop2_cmd(COP2_DPCS(1, 0));
521 int32_t mac1;
522 uint32_t rgb2, flag;
523 cop2_get(25, mac1);
524 cop2_get(22, rgb2);
525 flag = gte_read_flag();
526 ramsyscall_printf("DPCS FC<input: MAC1=%d RGB2=0x%08x FLAG=0x%08x\n", mac1, rgb2, flag);
527 // FC=0, R=0xFF: diff = (0<<12) - (0xFF<<16) = -0xFF0000 (negative)
528 // Inner clamp (lm=0): clamps to [-0x8000, 0x7FFF]
529 // Then IR0 * clamped_diff + R<<16 -> should produce intermediate result
530 cester_assert_int_eq(2040, mac1);
531 cester_assert_uint_eq(0x007f7f7f, rgb2);
532 cester_assert_uint_eq(0x00000000, flag);
533)
534
535// ==========================================================================
536// INTPL where FC < IR (interpolation goes backward)
537// ==========================================================================
538
539CESTER_TEST(edge_intpl_fc_less_than_ir, gte_tests,
540 gte_set_far_color(0, 0, 0); // FC = 0
541 cop2_put(9, 0x1000); // IR = 0x1000 (> FC)
542 cop2_put(10, 0x1000);
543 cop2_put(11, 0x1000);
544 cop2_put(8, 0x0800); // IR0 = 0.5
545 cop2_put(6, 0x00808080);
546 gte_clear_flag();
547 cop2_cmd(COP2_INTPL(1, 0));
548 int32_t mac1;
549 uint32_t flag;
550 cop2_get(25, mac1);
551 flag = gte_read_flag();
552 ramsyscall_printf("INTPL FC<IR: MAC1=%d FLAG=0x%08x\n", mac1, flag);
553 // IR=0x1000, FC=0, IR0=0.5
554 // diff = (0<<12) - (0x1000<<12) = -0x1000000
555 // inner clamp: -0x1000000 >> 12 = -0x1000 -> clamped to -0x1000 (in range)
556 // MAC = 0x1000<<12 + 0x800 * (-0x1000) = 0x1000000 + (-0x800000)
557 // >> 12 = (0x800000) >> 12 = 0x800 = 2048
558 cester_assert_int_eq(2048, mac1);
559 cester_assert_uint_eq(0x00000000, flag);
560)
COP2_INTPL
#define COP2_INTPL(sf, lm)
Definition cop2.h:142
cop2_cmd
#define cop2_cmd(op)
Definition cop2.h:175
COP2_GPL
#define COP2_GPL(sf, lm)
Definition cop2.h:169
COP2_V_V0
#define COP2_V_V0
Definition cop2.h:70
COP2_CV_NONE
#define COP2_CV_NONE
Definition cop2.h:79
cop2_put
#define cop2_put(reg, val)
Definition cop2.h:182
COP2_SQR
#define COP2_SQR(sf, lm)
Definition cop2.h:161
COP2_MX_RT
#define COP2_MX_RT
Definition cop2.h:64
COP2_GPF
#define COP2_GPF(sf, lm)
Definition cop2.h:168
COP2_NCLIP
#define COP2_NCLIP
Definition cop2.h:133
cop2_putc
#define cop2_putc(reg, val)
Definition cop2.h:196
COP2_RTPS
#define COP2_RTPS(sf, lm)
Definition cop2.h:129
COP2_AVSZ3
#define COP2_AVSZ3
Definition cop2.h:164
COP2_DPCS
#define COP2_DPCS(sf, lm)
Definition cop2.h:139
COP2_MVMVA
#define COP2_MVMVA(sf, mx, v, cv, lm)
Definition cop2.h:145
cop2_get
#define cop2_get(reg, dest)
Definition cop2.h:189
COP2_CV_TR
#define COP2_CV_TR
Definition cop2.h:76
mac1
int32_t mac1
Definition gte-edgecase.c:333
f21_255
uint32_t f21_255
Definition gte-edgecase.c:207
ramsyscall_printf
ramsyscall_printf("H=0: SX=%d FLAG=0x%08x\n", sx, flag)
gte_set_identity_rotation
gte_set_identity_rotation()
ir1
uint32_t ir1
Definition gte-edgecase.c:108
sz3
uint32_t sz3
Definition gte-edgecase.c:375
gte_set_far_color
gte_set_far_color(0, 0, 0)
sxy2
uint32_t sxy2
Definition gte-edgecase.c:36
f17
uint32_t f17
Definition gte-edgecase.c:44
cester_assert_uint_eq
cester_assert_uint_eq(0, f17)
f12
uint32_t f12
Definition gte-edgecase.c:483
f14
uint32_t f14
Definition gte-edgecase.c:291
gte_tests
gte_tests
Definition gte-edgecase.c:28
r_255
uint32_t r_255
Definition gte-edgecase.c:205
f18
uint32_t f18
Definition gte-edgecase.c:384
sx
int16_t sx
Definition gte-edgecase.c:39
r_neg
uint32_t r_neg
Definition gte-edgecase.c:241
flag
uint32_t flag
Definition gte-edgecase.c:36
mac2
int32_t mac2
Definition gte-edgecase.c:333
gte_set_translation
gte_set_translation(0, 0, 0)
cester_assert_int_eq
cester_assert_int_eq(0, sx)
gte_set_screen
gte_set_screen(0, 0, 0)
gte_clear_flag
gte_clear_flag()
ir0
uint32_t ir0
Definition gte-edgecase.c:478
CESTER_TEST
CESTER_TEST(edge_div_by_zero, gte_tests, gte_set_identity_rotation();gte_set_translation(0, 0, 0);gte_set_screen(0, 0, 200);cop2_put(0,(0<< 16)|100);cop2_put(1, 0);gte_clear_flag();cop2_cmd(COP2_RTPS(1, 0));uint32_t sz3, sxy2, flag;cop2_get(19, sz3);cop2_get(14, sxy2);flag=gte_read_flag();ramsyscall_printf("div/0: SZ3=%u SXY2=0x%08x FLAG=0x%08x\n", sz3, sxy2, flag);uint32_t f17=(flag > > 17) &1;cester_assert_uint_eq(1, f17);) CESTER_TEST(edge_div_h_zero
mac3
int32_t mac3
Definition gte-edgecase.c:333
f24
uint32_t f24
Definition gte-edgecase.c:114
rgb2
uint32_t rgb2
Definition gte-edgecase.c:202
mac0
int32_t mac0
Definition gte-edgecase.c:149
f21_neg
uint32_t f21_neg
Definition gte-edgecase.c:243
sy
int16_t sy
Definition gte-rtps.c:36
uint32_t
void uint32_t(classId, spec)
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