Nugget
Loading...
Searching...
No Matches
psyqo
hardware
cpu.hh
Go to the documentation of this file.
1
/*
2
3
MIT License
4
5
Copyright (c) 2023 PCSX-Redux authors
6
7
Permission is hereby granted, free of charge, to any person obtaining a copy
8
of this software and associated documentation files (the "Software"), to deal
9
in the Software without restriction, including without limitation the rights
10
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11
copies of the Software, and to permit persons to whom the Software is
12
furnished to do so, subject to the following conditions:
13
14
The above copyright notice and this permission notice shall be included in all
15
copies or substantial portions of the Software.
16
17
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23
SOFTWARE.
24
25
*/
26
27
#pragma once
28
29
#include "
psyqo/hardware/hwregs.hh
"
30
31
namespace
psyqo::Hardware::CPU
{
32
33
enum class
IRQ
:
uint32_t
{
34
VBlank
= 1 << 0,
35
GPU
= 1 << 1,
36
CDRom
= 1 << 2,
37
DMA
= 1 << 3,
38
Timer0
= 1 << 4,
39
Timer1
= 1 << 5,
40
Timer2
= 1 << 6,
41
Controller
= 1 << 7,
42
SIO
= 1 << 8,
43
SPU
= 1 << 9,
44
PIO
= 1 << 10,
45
};
46
47
template
<u
int
32_t offset>
48
struct
IRQReg
:
public
Register
<offset> {
49
void
set
(
IRQ
irq) { *
this
|= (
static_cast<
uint32_t
>
(irq)); }
50
void
clear
(
IRQ
irq) { *
this
&= ~(
static_cast<
uint32_t
>
(irq)); }
51
void
clear
() {
Register<offset>::access
() = 0; }
52
bool
isSet
(
IRQ
irq)
const
{
return
(*
this
&
static_cast<
uint32_t
>
(irq)) != 0; }
53
};
54
55
extern
IRQReg<0x0070>
IReg
;
56
extern
IRQReg<0x0074>
IMask
;
57
extern
Register<0x00f0>
DPCR
;
58
extern
Register<0x00f4>
DICR
;
59
60
extern
Register<0x0000, uint32_t, WriteQueue::Bypass>
WriteQueueFlusher
;
61
62
static
inline
void
flushWriteQueue() {
WriteQueueFlusher
.throwAway(); }
63
64
}
// namespace psyqo::Hardware::CPU
psyqo::CDRom
The base CDRom class.
Definition
cdrom.hh:46
psyqo::GPU
The singleton GPU class.
Definition
gpu.hh:88
psyqo::SPU
Definition
spu.hh:31
hwregs.hh
psyqo::Hardware::CPU
Definition
cpu.hh:31
psyqo::Hardware::CPU::IRQ
IRQ
Definition
cpu.hh:33
psyqo::Hardware::CPU::IRQ::DMA
@ DMA
psyqo::Hardware::CPU::IRQ::Timer1
@ Timer1
psyqo::Hardware::CPU::IRQ::PIO
@ PIO
psyqo::Hardware::CPU::IRQ::Controller
@ Controller
psyqo::Hardware::CPU::IRQ::Timer2
@ Timer2
psyqo::Hardware::CPU::IRQ::SIO
@ SIO
psyqo::Hardware::CPU::IRQ::VBlank
@ VBlank
psyqo::Hardware::CPU::IRQ::Timer0
@ Timer0
psyqo::Hardware::CPU::DPCR
Register< 0x00f0 > DPCR
Definition
cpu.cpp:31
psyqo::Hardware::CPU::IReg
IRQReg< 0x0070 > IReg
Definition
cpu.cpp:29
psyqo::Hardware::CPU::WriteQueueFlusher
Register< 0x0000, uint32_t, WriteQueue::Bypass > WriteQueueFlusher
Definition
cpu.cpp:35
psyqo::Hardware::CPU::DICR
Register< 0x00f4 > DICR
Definition
cpu.cpp:32
psyqo::Hardware::CPU::IMask
IRQReg< 0x0074 > IMask
Definition
cpu.cpp:30
psyqo::Hardware::CPU::IRQReg
Definition
cpu.hh:48
psyqo::Hardware::CPU::IRQReg::set
void set(IRQ irq)
Definition
cpu.hh:49
psyqo::Hardware::CPU::IRQReg::clear
void clear()
Definition
cpu.hh:51
psyqo::Hardware::CPU::IRQReg::clear
void clear(IRQ irq)
Definition
cpu.hh:50
psyqo::Hardware::CPU::IRQReg::isSet
bool isSet(IRQ irq) const
Definition
cpu.hh:52
psyqo::Hardware::Register
Definition
hwregs.hh:46
psyqo::Hardware::Register::access
volatile T & access(int index=0) const
Definition
hwregs.hh:162
uint32_t
void uint32_t(classId, spec)
Generated by
1.9.8