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cpu.hh
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1/*
2
3MIT License
4
5Copyright (c) 2023 PCSX-Redux authors
6
7Permission is hereby granted, free of charge, to any person obtaining a copy
8of this software and associated documentation files (the "Software"), to deal
9in the Software without restriction, including without limitation the rights
10to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11copies of the Software, and to permit persons to whom the Software is
12furnished to do so, subject to the following conditions:
13
14The above copyright notice and this permission notice shall be included in all
15copies or substantial portions of the Software.
16
17THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23SOFTWARE.
24
25*/
26
27#pragma once
28
30
32
33enum class IRQ : uint32_t {
34 VBlank = 1 << 0,
35 GPU = 1 << 1,
36 CDRom = 1 << 2,
37 DMA = 1 << 3,
38 Timer0 = 1 << 4,
39 Timer1 = 1 << 5,
40 Timer2 = 1 << 6,
41 Controller = 1 << 7,
42 SIO = 1 << 8,
43 SPU = 1 << 9,
44 PIO = 1 << 10,
45};
46
47template <uint32_t offset>
48struct IRQReg : public Register<offset> {
49 void set(IRQ irq) { *this |= (static_cast<uint32_t>(irq)); }
50 void clear(IRQ irq) { *this &= ~(static_cast<uint32_t>(irq)); }
52 bool isSet(IRQ irq) const { return (*this & static_cast<uint32_t>(irq)) != 0; }
53};
54
55extern IRQReg<0x0070> IReg;
56extern IRQReg<0x0074> IMask;
59
61
62static inline void flushWriteQueue() { WriteQueueFlusher.throwAway(); }
63
64} // namespace psyqo::Hardware::CPU
The base CDRom class.
Definition cdrom.hh:46
The singleton GPU class.
Definition gpu.hh:88
Definition spu.hh:31
Definition cpu.hh:31
IRQ
Definition cpu.hh:33
Register< 0x00f0 > DPCR
Definition cpu.cpp:31
IRQReg< 0x0070 > IReg
Definition cpu.cpp:29
Register< 0x0000, uint32_t, WriteQueue::Bypass > WriteQueueFlusher
Definition cpu.cpp:35
Register< 0x00f4 > DICR
Definition cpu.cpp:32
IRQReg< 0x0074 > IMask
Definition cpu.cpp:30
Definition hwregs.h:33
Definition cpu.hh:48
void set(IRQ irq)
Definition cpu.hh:49
void clear()
Definition cpu.hh:51
void clear(IRQ irq)
Definition cpu.hh:50
bool isSet(IRQ irq) const
Definition cpu.hh:52
Definition hwregs.hh:46
volatile T & access(int index=0) const
Definition hwregs.hh:162
void uint32_t(classId, spec)