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common
util
mips.hh
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/*
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MIT License
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Copyright (c) 2025 PCSX-Redux authors
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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*/
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#pragma once
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#include <stdint.h>
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namespace
Mips
{
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// clang-format off
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enum class
Reg
{
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R0
,
AT
,
V0
,
V1
,
A0
,
A1
,
A2
,
A3
,
// 00 to 07
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T0
,
T1
,
T2
,
T3
,
T4
,
T5
,
T6
,
T7
,
// 08 to 0f
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S0
,
S1
,
S2
,
S3
,
S4
,
S5
,
S6
,
S7
,
// 10 to 17
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T8
,
T9
,
K0
,
K1
,
GP
,
SP
,
S8
,
RA
,
// 18 to 1f
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};
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// clang-format on
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typedef
union
{
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struct
{
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uint32_t
r0, at, v0, v1,
a0
, a1, a2, a3;
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uint32_t
t0
, t1, t2, t3, t4, t5, t6, t7;
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uint32_t
s0
, s1,
s2
, s3, s4, s5, s6, s7;
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uint32_t
t8, t9, k0, k1,
gp
, sp, s8, ra;
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uint32_t
lo
,
hi
;
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} n;
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uint32_t
r
[34];
/* Lo, Hi in r[32] and r[33] */
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}
GPRRegs
;
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}
// namespace Mips
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// Make sure no packing is inserted anywhere
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static_assert
(
sizeof
(
Mips::GPRRegs
) == 34 *
sizeof
(
uint32_t
),
"GPRRegs size mismatch"
);
r
uint32_t r
Definition
cpu.c:222
lo
int32_t lo
Definition
cpu.c:154
Mips
Definition
decoder.hh:33
Mips::Reg
Reg
Definition
mips.hh:34
Mips::Reg::T8
@ T8
Mips::Reg::T5
@ T5
Mips::Reg::V0
@ V0
Mips::Reg::A1
@ A1
Mips::Reg::R0
@ R0
Mips::Reg::T9
@ T9
Mips::Reg::RA
@ RA
Mips::Reg::T3
@ T3
Mips::Reg::S7
@ S7
Mips::Reg::A3
@ A3
Mips::Reg::SP
@ SP
Mips::Reg::S1
@ S1
Mips::Reg::T6
@ T6
Mips::Reg::T2
@ T2
Mips::Reg::S5
@ S5
Mips::Reg::K1
@ K1
Mips::Reg::S6
@ S6
Mips::Reg::T0
@ T0
Mips::Reg::GP
@ GP
Mips::Reg::S8
@ S8
Mips::Reg::V1
@ V1
Mips::Reg::S2
@ S2
Mips::Reg::K0
@ K0
Mips::Reg::A2
@ A2
Mips::Reg::T1
@ T1
Mips::Reg::S4
@ S4
Mips::Reg::A0
@ A0
Mips::Reg::S3
@ S3
Mips::Reg::T7
@ T7
Mips::Reg::T4
@ T4
Mips::Reg::S0
@ S0
Mips::Reg::AT
@ AT
s2
static const char * s2
Definition
syscalls.h:91
uint32_t
void uint32_t(classId, spec)
Mips::GPRRegs
Definition
mips.hh:42
Mips::GPRRegs::t0
uint32_t t0
Definition
mips.hh:45
Mips::GPRRegs::a0
uint32_t a0
Definition
mips.hh:44
Mips::GPRRegs::gp
uint32_t gp
Definition
mips.hh:47
Mips::GPRRegs::s0
uint32_t s0
Definition
mips.hh:46
Mips::GPRRegs::hi
uint32_t hi
Definition
mips.hh:48
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