Nugget
Loading...
Searching...
No Matches
encoder.hh
Go to the documentation of this file.
1/*
2
3MIT License
4
5Copyright (c) 2021 PCSX-Redux authors
6
7Permission is hereby granted, free of charge, to any person obtaining a copy
8of this software and associated documentation files (the "Software"), to deal
9in the Software without restriction, including without limitation the rights
10to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11copies of the Software, and to permit persons to whom the Software is
12furnished to do so, subject to the following conditions:
13
14The above copyright notice and this permission notice shall be included in all
15copies or substantial portions of the Software.
16
17THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23SOFTWARE.
24
25*/
26
27#pragma once
28
29#include <stdint.h>
30
31#include "mips.hh"
32
33namespace Mips {
34namespace Encoder {
35
36using Reg = Mips::Reg;
37
38constexpr uint32_t iclass(uint32_t v) { return v << 26; }
39constexpr uint32_t dstVal(Reg r) { return uint32_t(r) << 11; }
40constexpr uint32_t tgtVal(Reg r) { return uint32_t(r) << 16; }
41constexpr uint32_t srcVal(Reg r) { return uint32_t(r) << 21; }
42
43// ALU
44constexpr uint32_t add(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100000; }
45constexpr uint32_t add(Reg dst, Reg tgt) { return add(dst, dst, tgt); }
46constexpr uint32_t addu(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100001; }
47constexpr uint32_t addu(Reg dst, Reg tgt) { return addu(dst, dst, tgt); }
48constexpr uint32_t addi(Reg tgt, Reg src, int16_t value) {
49 uint32_t v = value;
50 v &= 0xffff;
51 return iclass(0b001000) | srcVal(src) | tgtVal(tgt) | v;
52}
53constexpr uint32_t addi(Reg tgt, int16_t value) { return addi(tgt, tgt, value); }
54constexpr uint32_t addiu(Reg tgt, Reg src, int16_t value) {
55 uint32_t v = value;
56 v &= 0xffff;
57 return iclass(0b001001) | srcVal(src) | tgtVal(tgt) | v;
58}
59constexpr uint32_t addiu(Reg tgt, int16_t value) { return addiu(tgt, tgt, value); }
60constexpr uint32_t andd(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100100; }
61constexpr uint32_t andd(Reg dst, Reg tgt) { return andd(dst, dst, tgt); }
62constexpr uint32_t andi(Reg tgt, Reg src, uint16_t value) {
63 return iclass(0b001100) | srcVal(src) | tgtVal(tgt) | value;
64}
65constexpr uint32_t andi(Reg tgt, uint16_t value) { return andi(tgt, tgt, value); }
66constexpr uint32_t lui(Reg tgt, uint16_t value) { return iclass(0b001111) | tgtVal(tgt) | value; }
67constexpr uint32_t nor(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100111; }
68constexpr uint32_t nor(Reg dst, Reg tgt) { return nor(dst, dst, tgt); }
69constexpr uint32_t orr(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100101; }
70constexpr uint32_t orr(Reg dst, Reg tgt) { return orr(dst, dst, tgt); }
71constexpr uint32_t ori(Reg tgt, Reg src, uint16_t value) {
72 return iclass(0b001101) | srcVal(src) | tgtVal(tgt) | value;
73}
74constexpr uint32_t ori(Reg tgt, uint16_t value) { return ori(tgt, tgt, value); }
75constexpr uint32_t slt(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b101010; }
76constexpr uint32_t slt(Reg dst, Reg tgt) { return slt(dst, dst, tgt); }
77constexpr uint32_t sltu(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b101011; }
78constexpr uint32_t sltu(Reg dst, Reg tgt) { return sltu(dst, dst, tgt); }
79constexpr uint32_t slti(Reg tgt, Reg src, int16_t value) {
80 uint32_t v = value;
81 v &= 0xffff;
82 return iclass(0b001010) | srcVal(src) | tgtVal(tgt) | v;
83}
84constexpr uint32_t slti(Reg tgt, int16_t value) { return slti(tgt, tgt, value); }
85constexpr uint32_t sltiu(Reg tgt, Reg src, uint16_t value) {
86 return iclass(0b001011) | srcVal(src) | tgtVal(tgt) | value;
87}
88constexpr uint32_t sltiu(Reg tgt, uint16_t value) { return sltiu(tgt, tgt, value); }
89constexpr uint32_t sub(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100010; }
90constexpr uint32_t sub(Reg dst, Reg tgt) { return sub(dst, dst, tgt); }
91constexpr uint32_t subu(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100011; }
92constexpr uint32_t subu(Reg dst, Reg tgt) { return subu(dst, dst, tgt); }
93constexpr uint32_t xorr(Reg dst, Reg src, Reg tgt) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b100110; }
94constexpr uint32_t xorr(Reg dst, Reg tgt) { return xorr(dst, dst, tgt); }
95constexpr uint32_t xori(Reg tgt, Reg src, uint16_t value) {
96 return iclass(0b001110) | srcVal(src) | tgtVal(tgt) | value;
97}
98constexpr uint32_t xori(Reg tgt, uint16_t value) { return xori(tgt, tgt, value); }
99
100// shifts
101constexpr uint32_t sll(Reg dst, Reg tgt, uint16_t sa) { return dstVal(dst) | tgtVal(tgt) | (sa << 6) | 0b000000; }
102constexpr uint32_t sll(Reg dst, uint16_t sa) { return sll(dst, dst, sa); }
103constexpr uint32_t sllv(Reg dst, Reg tgt, Reg src) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b000100; }
104constexpr uint32_t sllv(Reg dst, Reg src) { return sllv(dst, dst, src); }
105constexpr uint32_t sra(Reg dst, Reg tgt, uint16_t sa) { return dstVal(dst) | tgtVal(tgt) | (sa << 6) | 0b000011; }
106constexpr uint32_t sra(Reg dst, uint16_t sa) { return sra(dst, dst, sa); }
107constexpr uint32_t srav(Reg dst, Reg tgt, Reg src) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b000111; }
108constexpr uint32_t srav(Reg dst, Reg src) { return srav(dst, dst, src); }
109constexpr uint32_t srl(Reg dst, Reg tgt, uint16_t sa) { return dstVal(dst) | tgtVal(tgt) | (sa << 6) | 0b000010; }
110constexpr uint32_t srl(Reg dst, uint16_t sa) { return srl(dst, dst, sa); }
111constexpr uint32_t srlv(Reg dst, Reg tgt, Reg src) { return dstVal(dst) | tgtVal(tgt) | srcVal(src) | 0b000110; }
112constexpr uint32_t srlv(Reg dst, Reg src) { return srlv(dst, dst, src); }
113
114// mults
115constexpr uint32_t div(Reg src, Reg tgt) { return tgtVal(tgt) | srcVal(src) | 0b011010; }
116constexpr uint32_t divu(Reg src, Reg tgt) { return tgtVal(tgt) | srcVal(src) | 0b011011; }
117constexpr uint32_t mfhi(Reg dst) { return dstVal(dst) | 0b010000; }
118constexpr uint32_t mflo(Reg dst) { return dstVal(dst) | 0b010010; }
119constexpr uint32_t mthi(Reg dst) { return dstVal(dst) | 0b010001; }
120constexpr uint32_t mtlo(Reg dst) { return dstVal(dst) | 0b010011; }
121constexpr uint32_t mult(Reg src, Reg tgt) { return tgtVal(tgt) | srcVal(src) | 0b011000; }
122constexpr uint32_t multu(Reg src, Reg tgt) { return tgtVal(tgt) | srcVal(src) | 0b011001; }
123
124// branches
125constexpr uint32_t beq(Reg src, Reg tgt, int16_t offset) {
126 uint32_t o = offset >> 2;
127 o &= 0xffff;
128 return iclass(0b000100) | tgtVal(tgt) | srcVal(src) | o;
129}
130constexpr uint32_t bgez(Reg src, int16_t offset) {
131 uint32_t o = offset >> 2;
132 o &= 0xffff;
133 return iclass(0b000001) | tgtVal(Reg(0b00001)) | srcVal(src) | o;
134}
135constexpr uint32_t bgezal(Reg src, int16_t offset) {
136 uint32_t o = offset >> 2;
137 o &= 0xffff;
138 return iclass(0b000001) | tgtVal(Reg(0b10001)) | srcVal(src) | o;
139}
140constexpr uint32_t bgtz(Reg src, int16_t offset) {
141 uint32_t o = offset >> 2;
142 o &= 0xffff;
143 return iclass(0b000111) | tgtVal(Reg(0b00000)) | srcVal(src) | o;
144}
145constexpr uint32_t blez(Reg src, int16_t offset) {
146 uint32_t o = offset >> 2;
147 o &= 0xffff;
148 return iclass(0b000110) | tgtVal(Reg(0b00000)) | srcVal(src) | o;
149}
150constexpr uint32_t bltz(Reg src, int16_t offset) {
151 uint32_t o = offset >> 2;
152 o &= 0xffff;
153 return iclass(0b000001) | tgtVal(Reg(0b00000)) | srcVal(src) | o;
154}
155constexpr uint32_t bltzal(Reg src, int16_t offset) {
156 uint32_t o = offset >> 2;
157 o &= 0xffff;
158 return iclass(0b000001) | tgtVal(Reg(0b10000)) | srcVal(src) | o;
159}
160constexpr uint32_t bne(Reg src, Reg tgt, int16_t offset) {
161 uint32_t o = offset >> 2;
162 o &= 0xffff;
163 return iclass(0b000101) | tgtVal(tgt) | srcVal(src) | o;
164}
165constexpr uint32_t brk(uint32_t code) { return (code << 6) | 0b001101; }
166constexpr uint32_t j(uint32_t addr) { return iclass(0b000010) | ((addr >> 2) & 0x03ffffff); }
167constexpr uint32_t jal(uint32_t addr) { return iclass(0b000011) | ((addr >> 2) & 0x03ffffff); }
168constexpr uint32_t jalr(Reg src, Reg dst = Reg::RA) { return dstVal(dst) | srcVal(src) | 0b001001; }
169constexpr uint32_t jr(Reg src) { return srcVal(src) | 0b001000; }
170constexpr uint32_t syscall() { return 0b001100; }
171
172// memory
173constexpr uint32_t lb(Reg tgt, int16_t offset, Reg src) {
174 uint32_t o = offset;
175 o &= 0xffff;
176 return iclass(0b100000) | tgtVal(tgt) | srcVal(src) | o;
177}
178constexpr uint32_t lbu(Reg tgt, int16_t offset, Reg src) {
179 uint32_t o = offset;
180 o &= 0xffff;
181 return iclass(0b100100) | tgtVal(tgt) | srcVal(src) | o;
182}
183constexpr uint32_t lh(Reg tgt, int16_t offset, Reg src) {
184 uint32_t o = offset;
185 o &= 0xffff;
186 return iclass(0b100001) | tgtVal(tgt) | srcVal(src) | o;
187}
188constexpr uint32_t lhu(Reg tgt, int16_t offset, Reg src) {
189 uint32_t o = offset;
190 o &= 0xffff;
191 return iclass(0b100101) | tgtVal(tgt) | srcVal(src) | o;
192}
193constexpr uint32_t lw(Reg tgt, int16_t offset, Reg src) {
194 uint32_t o = offset;
195 o &= 0xffff;
196 return iclass(0b100011) | tgtVal(tgt) | srcVal(src) | o;
197}
198constexpr uint32_t lwl(Reg tgt, int16_t offset, Reg src) {
199 uint32_t o = offset;
200 o &= 0xffff;
201 return iclass(0b100010) | tgtVal(tgt) | srcVal(src) | o;
202}
203constexpr uint32_t lwr(Reg tgt, int16_t offset, Reg src) {
204 uint32_t o = offset;
205 o &= 0xffff;
206 return iclass(0b100110) | tgtVal(tgt) | srcVal(src) | o;
207}
208constexpr uint32_t sb(Reg tgt, int16_t offset, Reg src) {
209 uint32_t o = offset;
210 o &= 0xffff;
211 return iclass(0b101000) | tgtVal(tgt) | srcVal(src) | o;
212}
213constexpr uint32_t sh(Reg tgt, int16_t offset, Reg src) {
214 uint32_t o = offset;
215 o &= 0xffff;
216 return iclass(0b101001) | tgtVal(tgt) | srcVal(src) | o;
217}
218constexpr uint32_t sw(Reg tgt, int16_t offset, Reg src) {
219 uint32_t o = offset;
220 o &= 0xffff;
221 return iclass(0b101011) | tgtVal(tgt) | srcVal(src) | o;
222}
223constexpr uint32_t swl(Reg tgt, int16_t offset, Reg src) {
224 uint32_t o = offset;
225 o &= 0xffff;
226 return iclass(0b101010) | tgtVal(tgt) | srcVal(src) | o;
227}
228constexpr uint32_t swr(Reg tgt, int16_t offset, Reg src) {
229 uint32_t o = offset;
230 o &= 0xffff;
231 return iclass(0b101110) | tgtVal(tgt) | srcVal(src) | o;
232}
233
234// cop0
235constexpr uint32_t mfc0(Reg tgt, uint8_t dst) { return iclass(0b010000) | tgtVal(tgt) | (dst << 11); }
236constexpr uint32_t mtc0(Reg tgt, uint8_t dst) { return iclass(0b010000) | (4 << 21) | tgtVal(tgt) | (dst << 11); }
237constexpr uint32_t rfe() { return 0x42000010; }
238
239// pseudo
240constexpr uint32_t nop() { return 0; }
241constexpr uint32_t li(Reg tgt, int16_t value) { return addiu(tgt, Reg::R0, value); }
242constexpr uint32_t liu(Reg tgt, uint16_t value) { return ori(tgt, Reg::R0, value); }
243constexpr uint32_t move(Reg tgt, Reg src) { return addu(tgt, Reg::R0, src); }
244constexpr uint32_t nott(Reg tgt, Reg src) { return nor(tgt, src, Reg::R0); }
245constexpr uint32_t nott(Reg tgt) { return nott(tgt, tgt); }
246constexpr uint32_t neg(Reg tgt, Reg src) { return subu(tgt, Reg::R0, src); }
247constexpr uint32_t neg(Reg tgt) { return neg(tgt, tgt); }
248constexpr uint32_t b(int16_t offset) { return bgez(Reg::R0, offset); }
249constexpr uint32_t beqz(Reg tgt, int16_t offset) { return beq(tgt, Reg::R0, offset); }
250constexpr uint32_t bnez(Reg tgt, int16_t offset) { return bne(tgt, Reg::R0, offset); }
251constexpr uint32_t bal(int16_t offset) { return bgezal(Reg::R0, offset); }
252
253} // namespace Encoder
254} // namespace Mips
uint32_t r
Definition cpu.c:222
constexpr uint32_t jr(Reg src)
Definition encoder.hh:169
constexpr uint32_t j(uint32_t addr)
Definition encoder.hh:166
constexpr uint32_t brk(uint32_t code)
Definition encoder.hh:165
constexpr uint32_t tgtVal(Reg r)
Definition encoder.hh:40
constexpr uint32_t mflo(Reg dst)
Definition encoder.hh:118
constexpr uint32_t srlv(Reg dst, Reg tgt, Reg src)
Definition encoder.hh:111
constexpr uint32_t mult(Reg src, Reg tgt)
Definition encoder.hh:121
constexpr uint32_t swr(Reg tgt, int16_t offset, Reg src)
Definition encoder.hh:228
constexpr uint32_t neg(Reg tgt, Reg src)
Definition encoder.hh:246
constexpr uint32_t slti(Reg tgt, Reg src, int16_t value)
Definition encoder.hh:79
constexpr uint32_t multu(Reg src, Reg tgt)
Definition encoder.hh:122
constexpr uint32_t addi(Reg tgt, Reg src, int16_t value)
Definition encoder.hh:48
constexpr uint32_t mfhi(Reg dst)
Definition encoder.hh:117
constexpr uint32_t lbu(Reg tgt, int16_t offset, Reg src)
Definition encoder.hh:178
constexpr uint32_t rfe()
Definition encoder.hh:237
constexpr uint32_t li(Reg tgt, int16_t value)
Definition encoder.hh:241
constexpr uint32_t lw(Reg tgt, int16_t offset, Reg src)
Definition encoder.hh:193
constexpr uint32_t sb(Reg tgt, int16_t offset, Reg src)
Definition encoder.hh:208
constexpr uint32_t bgtz(Reg src, int16_t offset)
Definition encoder.hh:140
constexpr uint32_t div(Reg src, Reg tgt)
Definition encoder.hh:115
constexpr uint32_t sll(Reg dst, Reg tgt, uint16_t sa)
Definition encoder.hh:101
constexpr uint32_t lui(Reg tgt, uint16_t value)
Definition encoder.hh:66
constexpr uint32_t addu(Reg dst, Reg src, Reg tgt)
Definition encoder.hh:46
constexpr uint32_t srcVal(Reg r)
Definition encoder.hh:41
constexpr uint32_t bltzal(Reg src, int16_t offset)
Definition encoder.hh:155
constexpr uint32_t andi(Reg tgt, Reg src, uint16_t value)
Definition encoder.hh:62
constexpr uint32_t jalr(Reg src, Reg dst=Reg::RA)
Definition encoder.hh:168
constexpr uint32_t jal(uint32_t addr)
Definition encoder.hh:167
constexpr uint32_t mtc0(Reg tgt, uint8_t dst)
Definition encoder.hh:236
Mips::Reg Reg
Definition encoder.hh:36
constexpr uint32_t mthi(Reg dst)
Definition encoder.hh:119
constexpr uint32_t beq(Reg src, Reg tgt, int16_t offset)
Definition encoder.hh:125
constexpr uint32_t lhu(Reg tgt, int16_t offset, Reg src)
Definition encoder.hh:188
constexpr uint32_t lwl(Reg tgt, int16_t offset, Reg src)
Definition encoder.hh:198
constexpr uint32_t bltz(Reg src, int16_t offset)
Definition encoder.hh:150
constexpr uint32_t subu(Reg dst, Reg src, Reg tgt)
Definition encoder.hh:91
constexpr uint32_t andd(Reg dst, Reg src, Reg tgt)
Definition encoder.hh:60
constexpr uint32_t mfc0(Reg tgt, uint8_t dst)
Definition encoder.hh:235
constexpr uint32_t sub(Reg dst, Reg src, Reg tgt)
Definition encoder.hh:89
constexpr uint32_t mtlo(Reg dst)
Definition encoder.hh:120
constexpr uint32_t sltiu(Reg tgt, Reg src, uint16_t value)
Definition encoder.hh:85
constexpr uint32_t swl(Reg tgt, int16_t offset, Reg src)
Definition encoder.hh:223
constexpr uint32_t srl(Reg dst, Reg tgt, uint16_t sa)
Definition encoder.hh:109
constexpr uint32_t sllv(Reg dst, Reg tgt, Reg src)
Definition encoder.hh:103
constexpr uint32_t bne(Reg src, Reg tgt, int16_t offset)
Definition encoder.hh:160
constexpr uint32_t move(Reg tgt, Reg src)
Definition encoder.hh:243
constexpr uint32_t xori(Reg tgt, Reg src, uint16_t value)
Definition encoder.hh:95
constexpr uint32_t nor(Reg dst, Reg src, Reg tgt)
Definition encoder.hh:67
constexpr uint32_t divu(Reg src, Reg tgt)
Definition encoder.hh:116
constexpr uint32_t beqz(Reg tgt, int16_t offset)
Definition encoder.hh:249
constexpr uint32_t syscall()
Definition encoder.hh:170
constexpr uint32_t nop()
Definition encoder.hh:240
constexpr uint32_t bgezal(Reg src, int16_t offset)
Definition encoder.hh:135
constexpr uint32_t add(Reg dst, Reg src, Reg tgt)
Definition encoder.hh:44
constexpr uint32_t sra(Reg dst, Reg tgt, uint16_t sa)
Definition encoder.hh:105
constexpr uint32_t xorr(Reg dst, Reg src, Reg tgt)
Definition encoder.hh:93
constexpr uint32_t lh(Reg tgt, int16_t offset, Reg src)
Definition encoder.hh:183
constexpr uint32_t sltu(Reg dst, Reg src, Reg tgt)
Definition encoder.hh:77
constexpr uint32_t addiu(Reg tgt, Reg src, int16_t value)
Definition encoder.hh:54
constexpr uint32_t lb(Reg tgt, int16_t offset, Reg src)
Definition encoder.hh:173
constexpr uint32_t blez(Reg src, int16_t offset)
Definition encoder.hh:145
constexpr uint32_t srav(Reg dst, Reg tgt, Reg src)
Definition encoder.hh:107
constexpr uint32_t ori(Reg tgt, Reg src, uint16_t value)
Definition encoder.hh:71
constexpr uint32_t nott(Reg tgt, Reg src)
Definition encoder.hh:244
constexpr uint32_t lwr(Reg tgt, int16_t offset, Reg src)
Definition encoder.hh:203
constexpr uint32_t sh(Reg tgt, int16_t offset, Reg src)
Definition encoder.hh:213
constexpr uint32_t bal(int16_t offset)
Definition encoder.hh:251
constexpr uint32_t orr(Reg dst, Reg src, Reg tgt)
Definition encoder.hh:69
constexpr uint32_t bnez(Reg tgt, int16_t offset)
Definition encoder.hh:250
constexpr uint32_t iclass(uint32_t v)
Definition encoder.hh:38
constexpr uint32_t bgez(Reg src, int16_t offset)
Definition encoder.hh:130
constexpr uint32_t sw(Reg tgt, int16_t offset, Reg src)
Definition encoder.hh:218
constexpr uint32_t slt(Reg dst, Reg src, Reg tgt)
Definition encoder.hh:75
constexpr uint32_t liu(Reg tgt, uint16_t value)
Definition encoder.hh:242
constexpr uint32_t dstVal(Reg r)
Definition encoder.hh:39
Definition decoder.hh:33
Reg
Definition mips.hh:34
char b[9]
Definition string.c:47
static int value
Definition syscalls.h:534
static const char * src
Definition syscalls.h:79
void uint32_t(classId, spec)