Nugget
Bare-metal libraries and examples for the original PlayStation
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slanted-gouraud.c
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1/*
2
3MIT License
4
5Copyright (c) 2026 PCSX-Redux authors
6
7Permission is hereby granted, free of charge, to any person obtaining a copy
8of this software and associated documentation files (the "Software"), to deal
9in the Software without restriction, including without limitation the rights
10to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11copies of the Software, and to permit persons to whom the Software is
12furnished to do so, subject to the following conditions:
13
14The above copyright notice and this permission notice shall be included in all
15copies or substantial portions of the Software.
16
17THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23SOFTWARE.
24
25*/
26
27// Slanted gouraud color suite. Every triangle here has BOTH the long
28// left edge and the top edge off-axis, so the per-row left-edge color
29// seed lands at a fractional x and the horizontal span delta both carry
30// truncated accumulators. That compounding is precisely what the
31// axis-aligned phase-7 gouraud suite cannot reach, and where a soft
32// renderer can drift by a single LSB on slanted gouraud fills.
33//
34// All probes target interior pixels or a covered (left) vertex; none
35// hit a top-left-excluded bottom/right vertex (those read sentinel).
36// SG_AB reproduces the exact triangle the 24 carried-over silicon
37// pixels were captured from, using full 8-bit 0xFF command colors (see
38// raster-expected-phase22.h).
39
40// clang-format off
41
43
44// SG_AB: the libgouraud cross-check triangle. Raw 0xFF command colors to
45// match the captured silicon. v0=(20,20)R v1=(200,60)G v2=(90,230)B.
46static void drawSGAB(void) {
47 rasterReset();
48 rasterClearTestRegion(0, 0, 64, 32);
49 rasterGouraudTri(0x0000ffu, 20, 20,
50 0x00ff00u, 200, 60,
51 0xff0000u, 90, 230);
52 rasterFlushPrimitive();
53}
54
55// SG1: medium slanted RGB triangle, suite idiom (5-bit colors).
56static void drawSG1(void) {
57 rasterReset();
58 rasterClearTestRegion(0, 0, 64, 56);
59 rasterGouraudTri(RASTER_CMD_RED, 8, 4,
60 RASTER_CMD_GREEN, 58, 22,
61 RASTER_CMD_BLUE, 22, 52);
62 rasterFlushPrimitive();
63}
64
65// SG2: flatter slanted RGB triangle, apex-low orientation.
66static void drawSG2(void) {
67 rasterReset();
68 rasterClearTestRegion(0, 0, 72, 56);
69 rasterGouraudTri(RASTER_CMD_RED, 40, 6,
70 RASTER_CMD_GREEN, 70, 48,
71 RASTER_CMD_BLUE, 6, 40);
72 rasterFlushPrimitive();
73}
74
75// SG_R: R-only slanted gradient. Apex R=31, base verts R=0. Isolates a
76// single channel's accumulator on a slanted shape.
77static void drawSGR(void) {
78 rasterReset();
79 rasterClearTestRegion(0, 0, 56, 56);
80 rasterGouraudTri(RASTER_CMD_RED, 6, 6,
81 0u, 54, 18,
82 0u, 18, 50);
83 rasterFlushPrimitive();
84}
85
86// SG3: narrow / steep slanted triangle.
87static void drawSG3(void) {
88 rasterReset();
89 rasterClearTestRegion(0, 0, 48, 56);
90 rasterGouraudTri(RASTER_CMD_RED, 30, 4,
91 RASTER_CMD_GREEN, 40, 50,
92 RASTER_CMD_BLUE, 20, 46);
93 rasterFlushPrimitive();
94}
95
96) // CESTER_BODY
97
98// --------------------------------------------------------------------------
99// SG_AB: 24 silicon cross-check probes
100// --------------------------------------------------------------------------
101
102CESTER_TEST(sg_ab_26_22, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_26_22, 26, 22); )
103CESTER_TEST(sg_ab_24_23, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_24_23, 24, 23); )
104CESTER_TEST(sg_ab_26_23, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_26_23, 26, 23); )
105CESTER_TEST(sg_ab_27_24, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_27_24, 27, 24); )
106CESTER_TEST(sg_ab_30_24, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_30_24, 30, 24); )
107CESTER_TEST(sg_ab_32_24, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_32_24, 32, 24); )
108CESTER_TEST(sg_ab_37_24, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_37_24, 37, 24); )
109CESTER_TEST(sg_ab_27_25, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_27_25, 27, 25); )
110CESTER_TEST(sg_ab_32_25, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_32_25, 32, 25); )
111CESTER_TEST(sg_ab_22_26, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_22_26, 22, 26); )
112CESTER_TEST(sg_ab_27_26, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_27_26, 27, 26); )
113CESTER_TEST(sg_ab_35_26, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_35_26, 35, 26); )
114CESTER_TEST(sg_ab_25_27, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_25_27, 25, 27); )
115CESTER_TEST(sg_ab_28_27, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_28_27, 28, 27); )
116CESTER_TEST(sg_ab_33_27, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_33_27, 33, 27); )
117CESTER_TEST(sg_ab_38_27, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_38_27, 38, 27); )
118CESTER_TEST(sg_ab_41_27, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_41_27, 41, 27); )
119CESTER_TEST(sg_ab_43_27, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_43_27, 43, 27); )
120CESTER_TEST(sg_ab_49_27, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_49_27, 49, 27); )
121CESTER_TEST(sg_ab_28_28, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_28_28, 28, 28); )
122CESTER_TEST(sg_ab_29_28, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_29_28, 29, 28); )
123CESTER_TEST(sg_ab_30_28, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_30_28, 30, 28); )
124CESTER_TEST(sg_ab_33_28, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_33_28, 33, 28); )
125CESTER_TEST(sg_ab_49_28, gpu_raster_phase22, drawSGAB(); ASSERT_PIXEL_EQ(SG_AB_49_28, 49, 28); )
126
127// --------------------------------------------------------------------------
128// SG1: medium slanted RGB triangle (interior probes)
129// --------------------------------------------------------------------------
130
131CESTER_TEST(sg1_29_26, gpu_raster_phase22, drawSG1(); ASSERT_PIXEL_EQ(SG1_29_26, 29, 26); )
132CESTER_TEST(sg1_24_24, gpu_raster_phase22, drawSG1(); ASSERT_PIXEL_EQ(SG1_24_24, 24, 24); )
133CESTER_TEST(sg1_36_28, gpu_raster_phase22, drawSG1(); ASSERT_PIXEL_EQ(SG1_36_28, 36, 28); )
134CESTER_TEST(sg1_20_20, gpu_raster_phase22, drawSG1(); ASSERT_PIXEL_EQ(SG1_20_20, 20, 20); )
135CESTER_TEST(sg1_30_32, gpu_raster_phase22, drawSG1(); ASSERT_PIXEL_EQ(SG1_30_32, 30, 32); )
136CESTER_TEST(sg1_40_24, gpu_raster_phase22, drawSG1(); ASSERT_PIXEL_EQ(SG1_40_24, 40, 24); )
137
138// --------------------------------------------------------------------------
139// SG2: flatter slanted RGB triangle (v2 covered vertex + interior)
140// --------------------------------------------------------------------------
141
142CESTER_TEST(sg2_v2_6_40, gpu_raster_phase22, drawSG2(); ASSERT_PIXEL_EQ(SG2_V2_6_40, 6, 40); )
143CESTER_TEST(sg2_39_31, gpu_raster_phase22, drawSG2(); ASSERT_PIXEL_EQ(SG2_39_31, 39, 31); )
144CESTER_TEST(sg2_30_30, gpu_raster_phase22, drawSG2(); ASSERT_PIXEL_EQ(SG2_30_30, 30, 30); )
145CESTER_TEST(sg2_48_32, gpu_raster_phase22, drawSG2(); ASSERT_PIXEL_EQ(SG2_48_32, 48, 32); )
146CESTER_TEST(sg2_40_20, gpu_raster_phase22, drawSG2(); ASSERT_PIXEL_EQ(SG2_40_20, 40, 20); )
147CESTER_TEST(sg2_20_34, gpu_raster_phase22, drawSG2(); ASSERT_PIXEL_EQ(SG2_20_34, 20, 34); )
148
149// --------------------------------------------------------------------------
150// SG_R: R-only slanted gradient (interior probes)
151// --------------------------------------------------------------------------
152
153CESTER_TEST(sgr_8_8, gpu_raster_phase22, drawSGR(); ASSERT_PIXEL_EQ(SGR_8_8, 8, 8); )
154CESTER_TEST(sgr_26_25, gpu_raster_phase22, drawSGR(); ASSERT_PIXEL_EQ(SGR_26_25, 26, 25); )
155CESTER_TEST(sgr_16_16, gpu_raster_phase22, drawSGR(); ASSERT_PIXEL_EQ(SGR_16_16, 16, 16); )
156CESTER_TEST(sgr_22_28, gpu_raster_phase22, drawSGR(); ASSERT_PIXEL_EQ(SGR_22_28, 22, 28); )
157CESTER_TEST(sgr_31_20, gpu_raster_phase22, drawSGR(); ASSERT_PIXEL_EQ(SGR_31_20, 31, 20); )
158CESTER_TEST(sgr_13_22, gpu_raster_phase22, drawSGR(); ASSERT_PIXEL_EQ(SGR_13_22, 13, 22); )
159
160// --------------------------------------------------------------------------
161// SG3: narrow / steep slanted triangle (v2 covered vertex + interior)
162// --------------------------------------------------------------------------
163
164CESTER_TEST(sg3_v2_20_46, gpu_raster_phase22, drawSG3(); ASSERT_PIXEL_EQ(SG3_V2_20_46, 20, 46); )
165CESTER_TEST(sg3_30_33, gpu_raster_phase22, drawSG3(); ASSERT_PIXEL_EQ(SG3_30_33, 30, 33); )
166CESTER_TEST(sg3_30_22, gpu_raster_phase22, drawSG3(); ASSERT_PIXEL_EQ(SG3_30_22, 30, 22); )
167CESTER_TEST(sg3_31_40, gpu_raster_phase22, drawSG3(); ASSERT_PIXEL_EQ(SG3_31_40, 31, 40); )
168CESTER_TEST(sg3_28_30, gpu_raster_phase22, drawSG3(); ASSERT_PIXEL_EQ(SG3_28_30, 28, 30); )
169CESTER_TEST(sg3_33_38, gpu_raster_phase22, drawSG3(); ASSERT_PIXEL_EQ(SG3_33_38, 33, 38); )
CESTER_TEST(cddaLevelHalf, test_instances, static const uint8_t atv[4]={0x40, 0x00, 0x40, 0x00};unsigned changes=0;int peak=cddaPeak(atv, 1, &changes);ramsyscall_printf("CD-DA level at half ATV: peak %i, %u sign changes\n", peak, changes);cester_assert_int_ge(peak, 11300);cester_assert_int_le(peak, 11800);cester_assert_uint_ge(changes, 4);) CESTER_TEST(cddaLevelClipped
CESTER_BODY(static uint16_t s_cddaCapture;static int cddaSpuDma(uint32_t spuAddr, void *buf, uint32_t bytes, int isRead) { const uint16_t tsa=spuAddr > > 3;const uint16_t mode=isRead ? 0x30 :0x20;SPU_RAM_DTA=tsa;for(int i=0;i< 0xf01 &&SPU_RAM_DTA !=tsa;i++);SPU_CTRL=(SPU_CTRL &~0x30)|mode;for(volatile int i=0;i< 60;i++);for(int i=0;i< 0xf01 &&(SPU_STATUS &0x30) !=mode;i++);CDDA_SPU_DELAY=(CDDA_SPU_DELAY &0xf0ffffff)|(isRead ? 0x22000000 :0x20000000);DMA_CTRL[DMA_SPU].MADR=(uint32_t) buf &0x1fffffff;DMA_CTRL[DMA_SPU].BCR=((bytes > > 6)<< 16)|0x10;DMA_CTRL[DMA_SPU].CHCR=isRead ? 0x01000200 :0x01000201;int ok=0;for(unsigned t=0;t< 4000000u;t++) { if((DMA_CTRL[DMA_SPU].CHCR &0x01000000)==0) { ok=1;break;} } SPU_CTRL=SPU_CTRL &~0x30;for(volatile int i=0;i< 60;i++);return ok;} static int cddaSimpleCmd(uint8_t cmd) { uint8_t response[16];CDROM_REG0=0;CDROM_REG1=cmd;uint32_t timeout=2000000;int ok=waitCDRomIRQWithTimeout(&timeout);ackCDRomCause();readResponse(response);return ok;} static void cddaWaitPauseComplete() { initializeTime();uint32_t elapsed=0;while(elapsed< 5000000u) { uint32_t budget=200000u;int ok=waitCDRomIRQWithTimeout(&budget);elapsed=budget;if(!ok) continue;uint8_t cause=ackCDRomCause();uint8_t response[16];readResponse(response);if(cause==2) return;} } static int cddaAudioSetup(const uint8_t atv[4], int demute) { if(!resetCDRom()) return 0;DPCR|=0x000b0000;SPU_CTRL=0;for(volatile int i=0;i< 20000;i++);SPU_VOL_MAIN_LEFT=0;SPU_VOL_MAIN_RIGHT=0;SPU_KEY_OFF_LOW=0xffff;SPU_KEY_OFF_HIGH=0xffff;SPU_RAM_DTC=4;SPU_CTRL=0x8001;for(volatile int i=0;i< 20000;i++);for(int i=0;i< 0x400;i++) s_cddaCapture[i]=CDDA_MARKER;if(!cddaSpuDma(0x000, s_cddaCapture, 0x800, 0)) return 0;if(!cddaSimpleCmd(demute ? CDL_DEMUTE :CDL_MUTE)) return 0;CDROM_REG0=2;CDROM_REG2=atv[0];CDROM_REG3=atv[1];CDROM_REG0=3;CDROM_REG1=atv[2];CDROM_REG2=atv[3];CDROM_REG0=3;CDROM_REG3=0x20;CDROM_REG0=0;SPU_VOL_CD_LEFT=0x7fff;SPU_VOL_CD_RIGHT=0x7fff;SPU_CTRL=SPU_CTRL|0x8001;return 1;} static int cddaBufferPeak(unsigned *signChanges) { int peak=0;unsigned changes=0;int prev=0;for(int i=0;i< 0x200;i++) { int v=(int16_t) s_cddaCapture[i];int a=v< 0 ? -v :v;if(a > peak) peak=a;int sign=v >=0 ? 1 :-1;if(i &&sign !=prev) changes++;prev=sign;} *signChanges=changes;return peak;} static int cddaCapturePeak(unsigned *signChanges) { int peak=0;for(unsigned attempt=0;attempt< 8;attempt++) { if(attempt) { initializeTime();while(updateTime()< 250000u);} if(!cddaSpuDma(0x000, s_cddaCapture, 0x800, 1)) return -1;peak=cddaBufferPeak(signChanges);if(peak) { if(attempt) ramsyscall_printf("capture was empty %u time(s) before audio\n", attempt);break;} } return peak;} static int cddaPeak(const uint8_t atv[4], int demute, unsigned *signChanges) { if(!cddaAudioSetup(atv, demute)) return -1;if(!setMode(0)) return -1;CDROM_REG0=0;CDROM_REG2=0x02;if(!cddaSimpleCmd(CDL_PLAY)) return -1;initializeTime();while(updateTime()< 1500000u);int peak=cddaCapturePeak(signChanges);CDROM_REG0=0;CDROM_REG1=CDL_PAUSE;cddaWaitPauseComplete();CDROM_REG0=0;CDROM_REG2=0x00;CDROM_REG2=0x02;CDROM_REG2=0x16;if(cddaSimpleCmd(CDL_SETLOC) &&cddaSimpleCmd(CDL_SEEKL)) cddaWaitPauseComplete();return peak;}[0x400])
Definition cdda.c:37
#define SG3_31_40
Definition raster-expected-phase22.h:136
#define SG_AB_33_28
Definition raster-expected-phase22.h:90
#define SG_AB_24_23
Definition raster-expected-phase22.h:69
#define SG_AB_43_27
Definition raster-expected-phase22.h:85
#define SG_AB_28_27
Definition raster-expected-phase22.h:81
#define SG_AB_30_28
Definition raster-expected-phase22.h:89
#define SG1_29_26
Definition raster-expected-phase22.h:97
#define SG2_39_31
Definition raster-expected-phase22.h:110
#define SG2_30_30
Definition raster-expected-phase22.h:111
#define SG_AB_27_25
Definition raster-expected-phase22.h:75
#define SGR_31_20
Definition raster-expected-phase22.h:125
#define SG_AB_28_28
Definition raster-expected-phase22.h:87
#define SGR_13_22
Definition raster-expected-phase22.h:126
#define SG_AB_29_28
Definition raster-expected-phase22.h:88
#define SG2_48_32
Definition raster-expected-phase22.h:112
#define SG_AB_30_24
Definition raster-expected-phase22.h:72
#define SG1_20_20
Definition raster-expected-phase22.h:100
#define SG_AB_38_27
Definition raster-expected-phase22.h:83
#define SG_AB_26_23
Definition raster-expected-phase22.h:70
#define SG_AB_25_27
Definition raster-expected-phase22.h:80
#define SG3_33_38
Definition raster-expected-phase22.h:138
#define SG_AB_27_26
Definition raster-expected-phase22.h:78
#define SG_AB_32_24
Definition raster-expected-phase22.h:73
#define SG_AB_27_24
Definition raster-expected-phase22.h:71
#define SG2_40_20
Definition raster-expected-phase22.h:113
#define SG_AB_32_25
Definition raster-expected-phase22.h:76
#define SG3_30_33
Definition raster-expected-phase22.h:134
#define SG1_24_24
Definition raster-expected-phase22.h:98
#define SG2_20_34
Definition raster-expected-phase22.h:114
#define SG_AB_26_22
Definition raster-expected-phase22.h:68
#define SG1_36_28
Definition raster-expected-phase22.h:99
#define SG_AB_37_24
Definition raster-expected-phase22.h:74
#define SG3_30_22
Definition raster-expected-phase22.h:135
#define SG_AB_49_28
Definition raster-expected-phase22.h:91
#define SG3_V2_20_46
Definition raster-expected-phase22.h:133
#define SG_AB_35_26
Definition raster-expected-phase22.h:79
#define SG_AB_49_27
Definition raster-expected-phase22.h:86
#define SG_AB_22_26
Definition raster-expected-phase22.h:77
#define SGR_8_8
Definition raster-expected-phase22.h:121
#define SG2_V2_6_40
Definition raster-expected-phase22.h:109
#define SGR_16_16
Definition raster-expected-phase22.h:123
#define SG1_40_24
Definition raster-expected-phase22.h:102
#define SG_AB_33_27
Definition raster-expected-phase22.h:82
#define SG3_28_30
Definition raster-expected-phase22.h:137
#define SGR_22_28
Definition raster-expected-phase22.h:124
#define SG1_30_32
Definition raster-expected-phase22.h:101
#define SG_AB_41_27
Definition raster-expected-phase22.h:84
#define SGR_26_25
Definition raster-expected-phase22.h:122
#define RASTER_CMD_BLUE
Definition raster-helpers.h:128
#define RASTER_CMD_RED
Definition raster-helpers.h:124
#define RASTER_CMD_GREEN
Definition raster-helpers.h:126
#define ASSERT_PIXEL_EQ(expected, x_, y_)
Definition raster-helpers.h:473